Current Server Time: 18:41 (Central Europe)

#apertus IRC Channel Logs

2016/05/31

Timezone: UTC


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John-K
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03:08
Bertl_oO
off to bed now ... have a good one everyone!
03:08
Bertl_oO
changed nick to: Bertl_zZ
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se6astian|away
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06:57
se6astian
good morning
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09:34
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10:22
danieel
Bertl_zZ: how can we programm just the fpga part of a zynq - via a command line tool? the arm part is not used
11:11
Bertl_zZ
changed nick to: Bertl
11:12
Bertl
morning folks!
11:12
Bertl
danieel: on the AXIOM Beta or in general?
11:20
danieel
in general, on ZC706
11:23
Bertl
okay, you need a JTAG programmer for that then
11:24
Bertl
you can use a tcl script for vivado to upload if you have the JTAG server running
11:25
Bertl
the commands can be found here: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/blink_done/vivado_upload.tcl
11:32
danieel
it has a programmer.. was hoping for something lightweight, to avoid installing vivado :)
11:33
Bertl
there is a special lab version available
11:33
Bertl
which is intended for programming and similar tasks, it is rather lightweight, but you can also use the ISE tools or any other JTAG programmer
11:34
Bertl
i.e. you can generate SVF files and use your favorite programmer
11:34
Bertl
(with an SVF player)
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se6astian
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se6astian|away
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John-K
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meg
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meg
Hello, Team Apertus!
17:28
Bertl
hello meg!
17:30
se6astian
hi meg :)
17:30
se6astian
what brings you to us?
17:31
meg
Interest in electronics
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RexOrCine
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17:32
Bertl
sounds good! :)
17:33
meg
I'm studying electronics engineering, how can I participate in this projects?
17:34
Bertl
in various ways I guess
17:34
Bertl
the first step is probably to get comfortable with the existing design
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meg
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mandresc
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illwieckz
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21:24
se6astian
I am off to bed
21:26
Bertl
nn
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se6astian
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jucar
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