Current Server Time: 20:58 (Central Europe)

#apertus IRC Channel Logs

2019/03/31

Timezone: UTC


00:21
Spirit532
left the channel
00:21
Spirit532
joined the channel
00:36
se6astian
changed nick to: se6astian|away
03:17
Bertl_oO
off to bed now ... have a good one everyone!
03:17
Bertl_oO
changed nick to: Bertl_zZ
04:06
futarisIRCcloud
joined the channel
08:05
illwieckz
left the channel
08:13
illwieckz
joined the channel
08:16
futarisIRCcloud
left the channel
08:51
se6astian|away
changed nick to: se6astian
08:53
futarisIRCcloud
joined the channel
09:03
se6astian
good day
09:57
BAndiT1983|away
changed nick to: BAndiT1983
10:34
mrohit[m]
good day se6astian
10:35
mrohit[m]
Hey BAndiT1983 , can you tell me what is the cooked.sh script doing exactly
10:38
mrohit[m]
* cooked .sh
11:06
futarisIRCcloud
left the channel
11:11
BAndiT1983
changed nick to: BAndiT1983|away
11:11
BAndiT1983|away
changed nick to: BAndiT1983
11:30
comradekingu
joined the channel
11:43
BAndiT1983
changed nick to: BAndiT1983|away
12:42
danieel
left the channel
12:45
se6astian
changed nick to: se6astian|away
13:30
BAndiT1983|away
changed nick to: BAndiT1983
14:02
parimal
joined the channel
14:05
parimal
left the channel
14:33
futarisIRCcloud
joined the channel
15:31
Bertl_zZ
changed nick to: Bertl_oO
15:49
BAndiT1983
changed nick to: BAndiT1983|away
15:49
BAndiT1983|away
changed nick to: BAndiT1983
16:13
shivamgoyal
joined the channel
16:29
BAndiT1983
changed nick to: BAndiT1983|away
16:50
shivamgoyal
left the channel
16:53
futarisIRCcloud
left the channel
17:23
Spirit532
left the channel
17:23
Spirit532
joined the channel
18:04
se6astian|away
changed nick to: se6astian
18:39
shivamgoyal
joined the channel
18:39
shivamgoyal
left the channel
19:11
aombk2
joined the channel
19:14
aombk
left the channel
19:51
apurvanandan[m]
Hi Bertl, In the project USB3.0 controller, once the controller for FT601Q is written in MACHXO2, where will we direct the data output from MACHXO2?
19:51
apurvanandan[m]
Will it be sent by packet protocol to main fpga?
19:52
apurvanandan[m]
ZYNQ Z7020
19:53
anuejn
I think you missunderstood it a bit
19:53
apurvanandan[m]
Please clear it
19:53
apurvanandan[m]
to me
19:53
anuejn
the task is about *reciving* data from the zynq and sending it via usb to a connected computer (mainly)
19:56
apurvanandan[m]
Oh sorry, I misinterpreted it.
19:56
felix_
https://github.com/enjoy-digital/pcie_screamer/blob/master/gateware/ft601.py might be worth a look for the ft60x interface. not sure how different the ft602 is from the ft601, but i'd expect that the only difference is the firmware
19:57
apurvanandan[m]
Actually there is much of verilog code available for FT601Q controller
19:57
apurvanandan[m]
I am reading and understanding those
19:59
apurvanandan[m]
So basically the task is just to send some test data from MACHOX2 and receive it correctly at the USB3.0 end?
20:04
apurvanandan[m]
or we would have some video data for this project because as far as I know, the communication protocol between the fpgas is not implmented yet
20:04
apurvanandan[m]
Am I right?
20:08
anuejn
no, I would interpret the task in a way, that requires sending video data
20:09
anuejn
without integration into the existing gateware, all that work would be much less useful imho
20:10
apurvanandan[m]
So how are we getting the video data from ZYNQ to MACH?
20:11
anuejn
well... that is the task, I guess
20:12
anuejn
you basically have 6 LVDS lanes and some (8) single ended ios
20:12
anuejn
which are routed in the plugin modules
20:13
anuejn
it might be easier to not use the single ended IOs bc. they are connected to andother machox2 (the routing fabric)
20:13
felix_
i'd either just use the hdmi output or use some sort of fifo interface over the differential pairs
20:14
anuejn
the routing fabric is lacking a finished firmware atm (see https://lab.apertus.org/T731)
20:14
anuejn
felix_:
20:14
anuejn
using the hdmi seems like a dirty hack to me
20:14
apurvanandan[m]
So is there some module currently on ZYNQ that sends video data on LVDS
20:14
apurvanandan[m]
?
20:15
anuejn
and it does not allow for streaming raw data
20:15
anuejn
so a fifo interface would be much nicer imho but also more work
20:16
apurvanandan[m]
fifo between the fpgas?
20:16
anuejn
apurvanandan[m]: no fifo interface or anything like that. only hdmi
20:17
felix_
sure, the fifo interface would be the better option, but the hdmi interface only requires work at one end and would work for up to 1080p60
20:17
anuejn
true
20:17
apurvanandan[m]
HDMI work on ZYNQ would have been already implemented no?
20:18
anuejn
but we need some other interface at some point of time anywas, so why not do it now ;)
20:18
anuejn
apurvanandan[m]: yes, the beta can already output hdmi
20:19
apurvanandan[m]
So we have two option either send by fifo to fifo or implement hdmi to fifo on MACHXO2?
20:20
apurvanandan[m]
FT601Q also receives fifo
20:21
anuejn
yup
20:23
apurvanandan[m]
We don't have place to connect the USB module directly to ZYNQ as two MACHXO2 will be connected already? Am I right?
20:42
apurvanandan[m]
The use of HDMI out from Zynq is only for testing purpose of the project no?
20:42
apurvanandan[m]
Later on you will use bidirectional packet protocol ?
20:46
BAndiT1983|away
changed nick to: BAndiT1983
21:19
felix_
the 8 single ended io pins on the axiom connector connect to the machxo2 on the camera; the 6 differential pairs connect dorectlt to the zynq. on the usb video module there's another machxo2 that sits between the ft602 (not 100% sure if it already is the 602 or still the 601 chip tbh) chip to deserialize the data from the zynq to feed it into the ft60x
21:20
danieel
joined the channel
21:20
felix_
the main video data flow is unidirectional (from the camera to the ft60x)
21:21
felix_
T731 is for the protocol between the zynq and the two machxo2 on the camera board and not the extension modules
22:01
apurvanandan[m]
Ok I got the idea
22:02
apurvanandan[m]
Is there something like a block diagram for whole system , so that I can get a better picture.
22:15
vup2
for a very high level overview you can take a look at these two: https://wiki.apertus.org/index.php/AXIOM_Beta/Manual#Image_Acquisition_Pipeline
22:16
se6astian
changed nick to: se6astian|away
22:16
vup2
but for anything more detailed i think you'll have to look at https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/peripherals/soc_main/top.vhd
22:16
vup2
and the related files
22:36
BAndiT1983
changed nick to: BAndiT1983|away
22:59
apurvanandan[m]
Ok thanks, what I didn't knew was there 2 lattice in main board and also lattice on plugin modules
23:58
aSobhy
hello Bertl :D
23:59
aSobhy
I have optimized my last code and changed the target fpga to max10
00:00
aSobhy
after optimization the speed reached 690 MHZ
00:01
aSobhy
but I dont know if that OK as on maxV you told me the emax speed is 300, So I am asking what is the minimum speed should I reach
00:03
aSobhy
*max speed*
00:08
aSobhy
Sorry for the long delay but the midterms had began :)
00:21
Bertl_oO
690 MHz on max10 sounds fine to me ... care to do any post implementation simulation and add the data as VCD file?
00:22
Bertl_oO
(runnign at 600MHz for example)
00:24
apurvanandan[m]
Hi Bertl
00:24
apurvanandan[m]
:)
00:51
Bertl_oO
hey
00:54
Bertl_oO
just to clarify the confusion about the USB 3.0 module:
00:54
Bertl_oO
the hardware can work perfectly fine in both directions, so it would be possible to use one USB 3.0 plugin for input and the other one for output
00:55
Bertl_oO
but the main focus of all the plugin modules is getting (sensor) data out of the camera