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04:04 | Bertl_oO | off to bed now ... have a good one everyone!
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06:45 | se6astian | good day
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12:22 | Bertl | morning folks!
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16:32 | tpw_rules | vup: alright i got vivado, yosys, and the naps libraries installed. i compiled the csr_demo applet, loaded it onto beta A, and tested with the pydriver console. it all worked great!
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16:32 | tpw_rules | i am impressed with how easy it was
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16:33 | tpw_rules | next i wanted to try the hdmi applet, but that is waiting on the recorder being set up. the first thing on my proposal is to implement sensor control, but that needs a sensor. are there any other SPI devices on the Beta i could experiment with first
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16:34 | tpw_rules | also i tried to run all the tests in naps, but a lot of them failed. is this expected or is there still something wrong with my installatiomn?
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16:45 | vup | tpw_rules: very nice, how do you like the pydriver stuff so far?
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16:48 | tpw_rules | i did not spend much time with it yet, but i am impressed by the simplicity. is it intended to be used by using the pydriver script that comes in the fatbitstream?
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16:48 | vup | yep
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16:49 | tpw_rules | and how does it work with simulation? is there a way to simulate the applets?
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16:49 | vup | I don't think there are suitable SPI devices on the main PCBs, but maybe Bertl has something he can quickly hook up, maybe to one of the plugin module slots?
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16:49 | vup | tpw_rules: we don't have generic simulation of arbitrary applets yet
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16:49 | vup | but all the infrastructure is basically there
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16:50 | tpw_rules | ok. i gather anuejn has been working on some sort of logic analyzer.
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16:50 | tpw_rules | debugging of all of this scares me a little bit :) but we can cross that bridge when we get there
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16:52 | vup | Re failing tests, usually there should be no failing tests, but it seems some recent yosys update broke something
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16:52 | tpw_rules | yes, lots of the tests seemed to be assertion failures in yosys
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16:52 | vup | we also have some formal tests, so for those you also need symbiyosys
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16:53 | tpw_rules | is there a way to use CSR stuff in simulation? this is my first time using CSR.
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16:53 | vup | you can compare your failing tests to the list here: https://github.com/apertus-open-source-cinema/naps/runs/2687022597
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16:53 | tpw_rules | i did not bother building yosys, i just downloaded and unpacked the fpga-toolchain archive like is done by the github actions
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16:54 | vup | tpw_rules: ah, then symbiyosys should be properly installed and you are probably hitting the same failures like the CI
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16:55 | tpw_rules | did a proposal get accepted to do nixos on the camera?
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16:55 | vup | tpw_rules: nobody was interested in working on it
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16:55 | tpw_rules | aww, i wanted to see that happen
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16:56 | vup | yeah, me too :)
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16:56 | tpw_rules | maybe i can do it next year
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16:56 | vup | sounds good :)
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16:56 | vup | now for simulation, currently we have no abstractions on the CSR level
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16:56 | vup | this means, to simulate a CSR read / write you need to use the "backend" implementation of the specific platform instead
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16:57 | vup | which is a convoluted way of saying, to test the CSRs on the zynq, you need to simulate AXI reads / writes
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16:58 | vup | finally there is now also a way to write simulations that look like the pydriver methods
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16:58 | vup | you can find a example of both here: https://github.com/apertus-open-source-cinema/naps/blob/5db701b5675ce8ab08b45b11492c1649ba3624a5/naps/cores/peripherals/soc_memory_test.py
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16:59 | tpw_rules | ok so this simsocplatform is what you guys use?
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16:59 | vup | SimSocPlatform is very new
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16:59 | vup | so it is not use very much yet
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16:59 | tpw_rules | i was thinking most of the simulations would be done at the individual module level anyway, like how i wrote the test for teh challenge
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16:59 | vup | we mostly use `platform.sim(...)` instead
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17:00 | tpw_rules | does naps have documentation anywhere? so far all i've found is doc/ which says "there is no docs" more or less :)
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17:00 | vup | no docs yet :(
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17:00 | tpw_rules | do docstrings get automatically dumped anywhere?
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17:00 | vup | we used to autogenerate sphinx docs
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17:00 | vup | but that broke aswell
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17:01 | tpw_rules | oh?
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17:01 | vup | you can find a old version here: https://apertus-open-source-cinema.github.io/naps/
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17:03 | vup | ```
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17:03 | vup | Exception occurred:
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17:03 | vup | File "/opt/hostedtoolcache/Python/3.8.10/x64/lib/python3.8/site-packages/sphinx/util/typing.py", line 303, in stringify
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17:03 | vup | elif annotation in INVALID_BUILTIN_CLASSES:
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17:03 | vup | TypeError: unhashable type: 'Shape'
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17:03 | vup | ```
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17:19 | Bertl | regarding SPI, we have the IMU CSO and the CSO adapter used on Beta B would allow to add that
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17:22 | vup | Bertl: but the CSO is connected to one of the machxo2's and not the zynq directly, right?
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17:22 | vup | or which adapter are you talking about?
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17:22 | Bertl | it is connected to both MachXO2s
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17:22 | Bertl | but not to the zynq, no
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17:23 | Bertl | but I doubt we will have any low speed (and SPI is low speed) interfaces on zynq I/Os
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17:24 | vup | yeah, I was more thinking along the lines of a plugin module breakout board -> hooking up some SPI device you have laying around
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17:25 | Bertl | well, I can check if I can find something
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17:25 | tpw_rules | wait, where is the sensor spi interface connected?
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17:26 | Bertl | on a full Beta, yes
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17:26 | tpw_rules | yes where?
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17:31 | vup | to the zynq
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17:31 | tpw_rules | ok
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17:34 | vup | (atleast in the current setup, its actually routed through another fpga, but that one currently just passes it through to the zynq)
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17:35 | tpw_rules | ok
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17:36 | tpw_rules | so what sort of procedures are there for design and code reviews, PRs, branching etc?
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17:39 | vup | I would say, try to submit self contained, not too big PRs, and then we will do code review via the github review thingy.
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17:40 | vup | anuejn and I have been doing most design review / discussion via vc, we could do the same if you are comfortable with that
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17:40 | tpw_rules | vc?
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17:40 | vup | video chat
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17:41 | tpw_rules | yeah that should work
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17:43 | vup | In general we will have our usual quick update meetings on mondays, and the gsoc meeting after that. This would be the place where I would like to make general plans for the rest of the week and general discussion about which steps to take next would take place.
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17:43 | tpw_rules | okay, that sounds good. so the first one would be tomorrow?
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17:44 | vup | Yes
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17:46 | tpw_rules | ok, see you then
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17:46 | vup | Now until either some test hardware for SPI or a actual sensor is setup, your first step could be adding the required resources to the platform definition we have for the beta: https://github.com/apertus-open-source-cinema/naps/blob/main/naps/platform/beta_platform.py
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17:46 | vup | you can do that by either digging through 5 layers of schematics here: http://files.apertus.org/HARDWARE/AXIOM/BETA/ :)
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17:47 | vup | or take the easy route and use the existing pin constraint files here https://github.com/apertus-open-source-cinema/axiom-firmware/tree/master/peripherals/soc_main
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17:48 | tpw_rules | those would go on the BetaPlatform class?
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17:48 | vup | yep
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17:49 | vup | ie add a resource that uses the connectors defined in the MicroZedZ020Plaform, which describes the sensor lvds and spi pins
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17:52 | tpw_rules | i am a little confused. the nmigen board definition describes JX1 and JX2. bertl shared these pictures of the Beta boards: https://i.imgur.com/eQv7sEr.jpg
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17:53 | tpw_rules | are JX1 and JX2 the two white horizontal connectors?
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17:53 | vup | no
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17:53 | vup | JX1 and JX2 are connectors on the microzed board, which is not visible on the picture
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17:54 | vup | maybe take a look at this: https://wiki.apertus.org/index.php/AXIOM_Beta/Camera_Structure
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17:54 | vup | the red pcb is the microzed
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17:55 | vup | which looks like this on the backside https://www.element14.com/community/themes/images/2019/microzed_back_view.jpg
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17:57 | vup | these are then passed through the pcb stack via first the powerboard, then the mainboard (which is what you see on the picture bertl shared), through a interface board and then to the sensor board
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18:00 | Bertl | off for now ... bbl
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18:00 | Bertl | changed nick to: Bertl_oO
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18:03 | tpw_rules | ok
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18:04 | tpw_rules | so i would be crossreferencing the pins here: https://github.com/apertus-open-source-cinema/axiom-firmware/blob/master/peripherals/soc_main/pin_cmv_ibc.xdc to the names in the JX1 and JX2 connectors in the board definition?
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18:04 | vup | yeah
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18:05 | tpw_rules | where are the non-lvds pins?
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18:07 | vup | https://github.com/apertus-open-source-cinema/axiom-firmware/blob/master/peripherals/soc_main/pin_spi_ibc.xdc for example
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18:07 | tpw_rules | oh, i missed the comment :)
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18:07 | vup | heh
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20:45 | anuejn | tpw_rules: yeah sometimes its a bit messy to debug all these layers of s*** ;)
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20:45 | anuejn | but when they work its quite comfy :)
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22:47 | anuejn | also the naps tests that were failing should be fixed now
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23:17 | vup | and even the vivado ci runner is now up again :)
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23:25 | anuejn | yay and found another nmigen bug :joy:
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