#apertus IRC Channel Logs

Ok so because there is a huge speed difference between the FPGAs this setup is the one that works out for the requirements for the AXIOM Beta?

yes, most of the IOs/protocols which will be active over the MachXO2s are really low speed, think I2C < 1Mbit, SPI < 10Mbit

ah, well, the challenge tasks are just to challenge you

so while 2 is on-topic, the others will also provide some insight for us about your coding/problem solving abilities

currently most of the additional GPIOs are either not working or bit-banged from python scripts

so with the full routing fabric protocol in place, we would gain plugin identification, CSO communication like for the IMU, etc

Ok so move a bunch of stuff directly to hardware?

Hmm okay with my current level of understanding these are the questions I had, I will dive deeper into the documentation and code work on the Challenge tasks and come up with a proposal ASAP so that I can get reviewed by the community.

Also a bit of background about myself, I graduated with a BS in EE in 2017 worked for 18 months in Microchips FPGA Division, 6 months in a startup that worked on Computer Vision on FPGA, and a few months on a research project involving an FPGA. I will be starting as a Masters student in University of Minnesota Twin Cities in Fall 2021, and am interested in this project because I am excited to get a chance to work with SERDES

Yeah

(and that's something, considering that the competitor tools are quite bad :)

interesting ... not sure why the microsemi folks then bothered discussing this in length

anyway, was for sure interesting working there ...

Microsemi sells to defence contractors

Same goes for Xilinx and Intel too.

if their customers ask them to open source it then they would consider it.

I am not exactly sure about the specifics tbh

Things is though the tools are ridiculous

For them getting the finished HW is more important. Struggling with tools is just part of the job

Bertl: Could I know more about the current status of the breakout board ? How should I be interfacing it with the routing fabric ?

yes

i.e. no logic there not even passive components

there is the Axiom Remote, our remote control device for the camera

https://wiki.apertus.org/index.php/AXIOM_Remote

this is roughly how the PCB looks like (at least for the original prototype)

i.e. add a remote control for the Axiom Remote ...

so that they can be 'pressed' electronically

we decided to put the Mosfets on a shield

so the Axiom Beta can now, using the routing fabric IOs, 'press' buttons and 'turn' knobs on the Axiom Remote

so the breakout board is simply screwed onto the bottom of the Axiom remote, and wires are soldered between the breakout board and the buttons, encoders, switches on the Axiom Remote

does that make sense now?

no problem, it's not easy to imagine if you do not see the setup

GSOC’21 WebUI task list

Task 2: Implement a WIFI configuration UI using NetworkManager

->Scan for WIFI networks

Task 5: Implement UI widgets for White balance & Gamma

Task 6: Implement UI for taking still photos with the Beta & Downloading them

Task 7: Implement A Hardware Overview Page that shows revisions of different the different board installed

vup Please help me understand task 5,6 and 7

did you already read the wiki camera documentation

and https://wiki.apertus.org/index.php/AXIOM_Beta_Firmware_Version_2.0

Task 6: UI with button/s to take snapshots, maybe also a list to present the files to the user for download

this is probably the more common for white balance: https://cam.start.canon/de/C003/manual/html/screens/UG-03_s0740.png

good morning 🙂