Current Server Time: 22:48 (Central Europe)

#apertus IRC Channel Logs

2020/03/30

Timezone: UTC


01:00
preetimenghwani[
I am confused you said the current remapper works in 32sensel mode what does that imply?
01:01
Bertl
that in our setup, 32 LVDS channels are connected and thus 32 channels produce input
01:01
Bertl
please check the CMV12000 datasheet to get an idea what I'm talking about
01:04
preetimenghwani[
Oh okay i read it once will read it again for better understanding thanks :)
01:04
Dest123
For the final goal "emulate sensor behaviour and bit stream", the different sensor components will have to be designed, SPI, sequencer, AFE,.....etc. right?
01:05
Bertl
yep
01:10
Dest123
For the image and video generation, is there some kind of a standard algorithm?
01:10
Bertl
maybe?
01:17
Dest123
Should it be generated based on something or the image can be random pixels with random values?
01:18
Bertl
well, purely random doesn't make much sense for testing
01:18
Bertl
pseudo random data is very valuable for testing
01:19
Bertl
but it is not suitable for all tests
01:21
Dest123
How can the pseudo random data be valuable while the random won't make sence? And when does it fail?
01:21
Bertl
true random data cannot be verified on the receiving side
01:22
Bertl
i.e. it is like noise
01:25
Dest123
I see
01:26
Bertl
off to bed now ... have a good one everyone!
01:26
Bertl
changed nick to: Bertl_zZ
01:28
Dest123
Good night
01:31
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05:59
BAndiT1983|away
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09:00
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11:43
Bertl_zZ
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11:43
Bertl
morning folks!
11:44
apoorva_arora
morning
11:52
omar31
morning Bertl
11:53
omar31
would you check my task please?
11:53
Bertl
url?
11:53
omar31
https://github.com/omar-joudi/high_speed_link
11:53
Bertl
tx
11:54
Bertl
Xilinx Zynq (LCMXO2-1200HC-6TG100C)
11:57
Bertl
there are some inconsistencies in the spacing for std_logic_vector ranges ... space vs no space before the () ... I do not mind which one you use but you should use it consistently
11:59
omar31
> Xilinx Zynq (LCMXO2-1200HC-6TG100C)
11:59
omar31
sorry, fixed it
11:59
Bertl
there are also some lines which go way beyond the maximum line length ... (using 4 spaces instead of a tab might help a little)
12:00
omar31
ok, will fix them
12:01
Bertl
when you write 'tested on' did you actually run it on the listed hardware?
12:03
omar31
no actually I have some timing violations that I wish you could give me hints on how to solve them
12:03
Bertl
tp.vhd (type in name?) has some indentation issues as well
12:06
Bertl
in your timing_report.txt, do you know what the line 'Timing constraints are not met.' means?
12:08
BAndiT1983|away
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12:09
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12:10
omar31
there are paths that fail to meet the timing
12:10
omar31
due to excessive path delay
12:11
Bertl
what does that mean for the implementation?
12:12
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12:13
omar31
it will not work?
12:15
Bertl
yep, okay
12:17
Bertl
Diamond clocks out at slightly over 100MHz with your design too, so not really high speed yet
12:23
omar31
I think sampling at both edges causes problems, I could reach more than double of this frequency with single edge
12:24
Bertl
did you look into high speed interfaces for both FPGAs?
12:27
preetimenghwani[
Bertl: For changing modes in CMV12000 programming of sequencer register is required using SPI interface do we need to take care of that also?
12:27
omar31
Bertl: Yes, I took a look at them
12:29
Bertl
preetimenghwani[: the SPI programming happens from the Zynq/Linux side so you can assume that the sensor SPI registers are programmed accordingly
12:30
Bertl
but the Zynq also needs to configure the remapper according to the set sensor parameters :)
12:30
Bertl
omar31: any ideas how to improve the situation or is 200MHz (the version you had without DDR) the upper limit?
12:33
omar31
Maybe I can use pipelining but this will affect the time which data takes to arrive
12:37
Bertl
you know Lattice TN1203?
12:41
omar31
yes that is the high speed interface notes that I said I had a look at
12:46
Bertl
so, might any of those solutions apply here?
12:57
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13:00
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13:03
omar31
Bertl: I am already using PLL and DDR, so I do not think an additional block can be integrated with them
13:10
preetimenghwani[
Bertl: To synchronize zynq with LVDS outputs, training pattern is used is that you mean here?
13:47
Bertl
omar31: so what you are basically saying is that the MachXO2 is not capable of transmitting or receiving data at more than 200Mbit or so?
13:47
Bertl
preetimenghwani[: no, but maybe we are talking about different things here, please rephrase your question
13:53
preetimenghwani[
You said zynq needs to be configure the remapper how can that be achieved?
13:54
preetimenghwani[
Also it is necessary to to synchronize zynq with the LVDS using training pattern testing on hardware right?
13:58
omar31
Bertl: In the current design the data is decoded after half cycle of the slow clock
13:59
omar31
I think the frequency can be increased at the expense of this time
14:05
Bertl
preetimenghwani[: configuration should happen via some kind of register interface similar to the existing features
14:05
Bertl
synchronization and deserialization (including link training already happens, but could be improved of course
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14:22
preetimenghwani[
Okay
14:22
preetimenghwani[
And also in discription of current remapper it says that one LVDS pin gives out 1 pixel in 1 clock cycle but the pins can give only 1 bit output at a time right?
14:29
Bertl
correct
14:29
Bertl
check the CMV12000 data sheet for all the gory details how the sensel data is transferred
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17:02
max_bxl
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17:02
max_bxl
hello everyone!
17:02
BAndiT1983
hi max_bxl
17:02
se6ast1an
hi therre
17:02
se6ast1an
meeting tme!
17:02
se6ast1an
who is here?
17:02
max_bxl
I am!
17:03
se6ast1an
great
17:03
se6ast1an
maxime do you want to start with reporting?
17:03
max_bxl
why not
17:03
max_bxl
nothing much to report
17:03
Bertl
is here ...
17:03
max_bxl
we try to do a night time liapse
17:03
max_bxl
but it happens it was too cloudy
17:03
max_bxl
to make any conclusions....
17:04
se6ast1an
is the "old" timelase where you shared 1 second done now?
17:04
max_bxl
and I put a link to the ambrosia wiki page
17:04
max_bxl
so you can see the results as we process them and dowload the raw12 to play with them
17:05
max_bxl
check for yourself !https://wiki.apertus.org/index.php/Project_Ambrosia#Media
17:05
max_bxl
I still need to make some space on my hard drive in order to reprocess the stopmotion raw image sequence
17:06
max_bxl
(the raw12 of the second TL are not online as it was not that interesting)
17:06
max_bxl
I had two questions, but maybe after all the reports?
17:07
se6ast1an
great, yes tech questions afterwards sounds good to keep the reports brief
17:07
max_bxl
ok, so that about it for me to report
17:07
max_bxl
hopefully more to come next week ;)
17:08
se6ast1an
great, thanks
17:08
se6ast1an
BAndiT1983: anything to share?
17:08
BAndiT1983
just a bit
17:08
BAndiT1983
managing gsoc related stuff, trying to check the progress of students
17:09
BAndiT1983
besides that writing a script for automatic PCB inspection for Bertl, most parts done, but bug fixing takes time
17:09
BAndiT1983
other than that making plans for BL and firmware, but had no time to continue yet
17:09
BAndiT1983
that's all for now
17:09
max_bxl
BL?
17:10
BAndiT1983
bootloader, sorry am used to shorten it
17:10
max_bxl
thanks
17:10
max_bxl
(I need to learn ^^)
17:10
Oscar
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17:11
vup
is also here
17:11
se6ast1an
great, hi vup and oscar
17:11
Oscar
Hi!
17:11
se6ast1an
Bertl will share more about this inspection idea I assume when its his turn
17:12
se6ast1an
thanks BAndiT1983
17:12
se6ast1an
vup any progress to report with the micro?
17:13
vup
well, we continued working on the new hardware, and have now planned the power subsystem
17:13
vup
but other than than, nothing new
17:13
vup
(the new hardware revision is currently developed at https://github.com/axiom-micro/mainboard/tree/r3 if you want to check it out, but not much documentation / images done yet)
17:14
se6ast1an
did you and Bertl plan an ecp5 plugin module already?
17:14
se6ast1an
as was hinted at last irc meeting IIRC
17:15
vup
not yet
17:15
Bertl
I did some checks and investigated our options regarding escape
17:15
Bertl
we definitely need 4mil trace and 7mil vias for the 17x17mm BGA
17:16
Bertl
and we would require 4mil trace, 4mil vias for the 10x10mm BGA package
17:16
Bertl
but four layers should be enough
17:16
vup
are you sure re 7mil vias?
17:17
vup
to me it seemed like 0.2mm would also work
17:17
Bertl
no, but that's what the Lattice Package documentation says :)
17:17
se6ast1an
very interesting, thanks
17:17
vup
(of course depending on minimum via to pad / trace spacing)
17:17
se6ast1an
anything else vup?
17:17
Bertl
but we can discuss that later I guess
17:17
se6ast1an
yes tech details after reporting please
17:18
vup
nothing else from me
17:18
se6ast1an
right, thank you!
17:18
vup
ah I think anuejn started working on usb uvc support in the recorder (for example for the camlink 4k)
17:18
se6ast1an
ah great
17:18
vup
but not sure how far he got there
17:18
se6ast1an
oscar, anything to report from your side?
17:21
se6ast1an
or Bertl are you ready with the images you mentioned?
17:21
Bertl
yeah, I think I'm ready
17:21
se6ast1an
great, please go ahead
17:22
Bertl
so, besides the usual business (rework, design, planning, etc), and a quite intensive GSoC application week
17:22
Bertl
I did write together the bullet points for the Axiom Beta Power Boards (feature list) as urgently requested by RexOrCine
17:23
Bertl
and I also added new board renders for all three Power Board branches we currently have
17:24
Bertl
i.e. for the v0.30 we have been using till now, the upcoming v1.x and the future v2.x
17:24
Bertl
had to adjust the renderer somewhat because of the obvious ImageMagick changes in v7
17:25
se6ast1an
results have partially been published here already: https://wiki.apertus.org/index.php/Beta_Power_Board
17:25
Bertl
After the v1.x power board tests went smoothly last week, I decided to build a complete prototype, but I didn't want to probe the PCBs by hand (before populating them)
17:26
Bertl
so (already last week) the automated testing was revived
17:26
Bertl
the basic concept here for a start is to do a single probe testing
17:27
Bertl
now how is this going to work you might ask yourself?
17:27
Bertl
it actually isn't just a single probe, but we'll get that shortly
17:27
Bertl
so to simplify things, I decided to adapt a 3D printer (Creality Ender-2) for this specific task
17:28
Bertl
I removed the filament feeder, the hot-end, the LCD (who needs that anyway? :), replaced the noisy power supply with a relatively silent PC power supply (no hotbed heating required)
17:29
se6ast1an
reference: https://www.apertus.org/diy-flying-probe-AOI
17:29
Bertl
I improved a number of things on the Ender-2 as well, mostly with existing MODS but also with some new designs
17:30
Bertl
the entire test setup, done under lab conditions, looks like this:
17:30
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_151918.jpg
17:30
BAndiT1983
are all the guys also paying the apartment rent?
17:31
Bertl
modifications included: an elevated Z-limit switch and spacer for the Z-stepper: http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_152154.jpg
17:31
BAndiT1983
what is the shorter pogo pin doing?
17:31
Bertl
I'll come to that in a minute :)
17:31
BAndiT1983
ah
17:31
Bertl
a Z-axis stabilisation with ball bearing: http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_152513.jpg
17:32
Bertl
(probbly not required for this task, but that was one of the first Ender-2 modifications I did
17:32
Bertl
and finally a stabilization for the hot-bed, which is simply done via nuts
17:33
Bertl
now the removed hot-end was replaced by a base plate (here in blue) where the probe(s) can be attached:
17:33
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_152625.jpg
17:34
Bertl
on the left side, there is an usb microscope (good quality) for precision positioning: http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_152356.jpg
17:34
Bertl
which can be adjusted in height and focus quite easily but is rigidly mounted
17:35
BAndiT1983
is the view field wide enough to see the probe?
17:35
Bertl
no, I'll provide some screenshots from that later
17:35
Bertl
the probe itself has a 'known' offset to the camera position, so it is simply a matter of adding/subtracting that offset
17:36
Bertl
now to the probe itself: http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_152415.jpg
17:36
Bertl
as you already noticed, there are two probes not just one, but one is currently unused
17:36
Bertl
I wasn't sure which pogo-pin size would be best for this purpose, so I added two pogo-pin holder for two different sizes
17:37
Bertl
if you look closely, you'll see that the tiny pogo-pin is in a holder as well, so it can be easily replaced
17:37
Bertl
note: there are different probe heads so switching them out makes sense and we'll se what works best
17:38
Bertl
the probes are attached to a PIC microconrtoller which in turn connects via an FTDI serial to usb converter
17:38
Bertl
the PIC can be reprogrammed via this converter and also provides probe information via the serial connetion
17:39
BAndiT1983
reprogrammed?
17:39
BAndiT1983
are you generating singals from the PC?
17:39
BAndiT1983
*signals
17:39
Bertl
now the PCB itself is simply mounted on four spacers (the white thigies): http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_151935.jpg
17:40
Bertl
and taped to the bed, so that the board has a known elevation and doesn't move around
17:40
Bertl
BAndiT1983: yes, everything is currently controlled from a PC/laptop
17:41
Bertl
now the idea behind the white spacer is what makes the single probe probing useful
17:41
Bertl
if you look closely at it on this image: http://vserver.13thfloor.at/Stuff/AXIOM/PROBE/IMG_20200330_152702.jpg
17:41
Bertl
you can see that there is a gap at the edge and the spacer goes into the plated hole in the corner of the PCB
17:42
Bertl
you can easily put a flexible wire in there and make a reliable connection to this plated hole
17:42
Bertl
on basically all our PCBs, the plated corner mounting holes are connected to ground, so this gives a good ground connection to the entire PCB
17:43
Bertl
the probe can now use two different probing methods depending on the to-be-probed pads
17:43
Bertl
one is to simply detect the gound connection (either wanted or unwanted)
17:44
Bertl
and the other is by using a nifty trick of the ADC available in the PIC MCU
17:44
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17:44
Bertl
basically an ADC consists of a sampling capacitor and a circuitry to convert the voltage on that capacitor to bits
17:45
Bertl
now the probing used here works like this:
17:45
Bertl
first the capacitor is charged to a well known voltage generated by the fixed voltage reference in the PIC
17:45
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17:46
Bertl
then the probe pin is tied to ground, to ensure that the pad is at a known voltage level as well (0)
17:46
Bertl
then the probe pin is set to floating and the sampling capacitor from the ADC is connected to the pin
17:47
Bertl
this connects the capacitance from the probe (pad and trace) with the sampling capacitor, creating a capacitive voltage divider
17:47
Bertl
and the resulting voltage can be digitized by the ADC
17:48
Bertl
we'll see how good that works but preliminary test were promising
17:49
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17:49
se6ast1an
is this following the concept discussed at the time? was called something like "one-probe..." analogue measuring?
17:49
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17:51
se6ast1an
and if it is do you need reference measurements or can you also test "the first board" properly?
17:52
Bertl
well, yes and no
17:52
Bertl
we can do all the is ground or isn't ground tests on the first one
17:52
Bertl
and they will weed out most of the problems we had so far
17:53
Bertl
for the more advanced testing we need to compare the results between boards
17:53
Bertl
but for prototyping, as we always get 3 boards, it should be fairly easy to spot issues
17:53
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17:53
se6ast1an
right, many thanks!
17:53
se6ast1an
anything else to add?
17:53
Bertl
also note that the concept we discussed back then (analog probe)
17:54
Dest123
Hello :)
17:54
Bertl
is not exactly what we do right now, because we do not test with a pulse but instead just use capacitive measurements
17:54
Bertl
(so a rather simple method compared to the envisioned, but a good start IMHO)
17:54
se6ast1an
understood, great
17:55
BAndiT1983
is resistance also planned or not relevant?
17:55
Bertl
I'm currently working on attaching a pi-zero with camera
17:55
Bertl
so that the probe in action can be observed as well
17:56
Bertl
resistance on a brand new PCB is not really that interesting, but we could measure that as well with the existing probe (at least to ground)
17:56
Bertl
by simply configuring a pullup and digitizing the resulting voltage
17:57
Bertl
next step is to test the probing with the pad information generated from BAndiT1983's script
17:57
Bertl
if there are any questions, please talk to me after the meeting
17:58
Bertl
that's it from my side for this week
17:58
se6ast1an
many thanks
17:58
se6ast1an
anyone else here in the meantime who wants to share/report and didnt so far?
17:58
se6ast1an
otherwise quick updates from me:
17:59
Bertl
note: applicants are welcome to participate as well
17:59
se6ast1an
next gsoc deadline is approaching fast, student application deadline is tomorrow on the 31st - more details: https://developers.google.com/open-source/gsoc/timeline
17:59
se6ast1an
google delayed some later deadlines due to corona virus as a lot of universities are being closed all over the world right now...
17:59
BAndiT1983
hope that students have got the paper work done befor that
17:59
BAndiT1983
*before
18:00
se6ast1an
hopefully
18:00
se6ast1an
for the AXIOM Remote I modified the LCD holder (3d print part) to also hold Bertls additional remote control PCB below: https://cad.onshape.com/documents/12bc6fbd9b32fa10f6c16ff9/w/2b05098c1a8a2447a85fcae9/e/54a0b5d91cb3d6a04f899f00
18:00
se6ast1an
and we ordered 10 lcds for the remote a few days ago
18:00
se6ast1an
PCB quotes collection progress is sluggish as suppliers have non engineers do all the customer communication and sales and so they mostly do not understand the technical requirements we have - its always one step forward, two steps back and then two steps forward....hopefully
18:01
se6ast1an
I made some CAD design progress: https://cloud.apertus.org/index.php/apps/gallery/s/jycWfbwpWYAwfJ6
18:01
se6ast1an
in particular with the HDMI holder clamp, microphone holder attachment points and now with attaching the AXIOM Remote to the camera together with an NP-F battery. All in concept phase still but progressing.
18:01
se6ast1an
with the powerboard additions Bertl is currently verifying we will be able to do some battery capacity monitoring through voltage/current measurements
18:02
se6ast1an
thats it from me
18:03
se6ast1an
if nobody else has any topics I would conclude the meeting and invite you to discuss the technical details we held back during the meeting
18:04
se6ast1an
meeting concluded!
18:04
se6ast1an
many thanks for being here and participating!
18:04
Bertl
thanks for having us!
18:04
se6ast1an
another great week done, another wonderful one to go :)
18:04
Bertl
\o/
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18:16
Oscar
See you all! (@Sebastian I was called away for a phone call so I couldn't relpy)
18:16
max_bxl
see you!
18:18
max_bxl
my technical question was : how to window the sensor when taking snaps (with axiom-snap) in order to have for example only 4096x2048px raw12 ?
18:19
max_bxl
or even 2048x1536px ?
18:19
Bertl
it probably will work out of the box if you set the registers correctly
18:20
max_bxl
I find out how to set registers with axiom-cmv-reg.sh
18:20
Bertl
it might be necessary to adjust the address generator and maybe adapt the cmv_snap3 to handle the window
18:21
Bertl
but I plan to update cmv_snap soon so it might make sense to put a wish list on a lab task :)
18:21
Bertl
(well, soon-is :)
18:21
Bertl
*ish
18:21
max_bxl
ok!
18:26
max_bxl
done : https://lab.apertus.org/T1168
18:30
Bertl
good start, still needs some love :)
18:36
max_bxl
updated ;)
18:38
Bertl
lol
18:39
Bertl
what I meant was a description what features to add like for example vertical windowing etc
18:39
Bertl
a width of 2048 requires either subsampling or binning for example as there is no horizontal windowing
18:47
Oscar
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18:57
max_bxl
from what I read from the datasheet, binning helps to reduce noise, right ?
18:57
max_bxl
that's the main advantage over subsampling ?
19:07
max_bxl
ok, I elaborated a bit the idea
19:07
max_bxl
off for now, bye !
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20:20
Dest123
Hey bertl, I have a couple of questions if you are free
20:21
Bertl
sure, go ahead
20:21
Dest123
What is the use of the digital offset in the CMV12k
20:23
Bertl
it adjusts the dark level
20:27
Dest123
What about the amplifier? Why would I want to add an analog gain to the pixel?
20:33
se6ast1an
to make the image brighter
20:38
Bertl
to get the best out of the sensor, you want to cover a good portion of the digital (ADC) range
20:39
Bertl
e.g. if you have 10 bit, you have values from 0 to 1023, so it is good to have the analog output cover this range, e.g. from 42 to 987
20:39
Bertl
instead of just from 23 to 234 for example
20:40
Bertl
this is where the gain amplifier comes in
20:41
Dest123
I see
20:41
Dest123
Thank you
20:41
Bertl
you're welcome!
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Bertl
off for now ... bbl
21:24
Bertl
changed nick to: Bertl_oO
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preetimenghwani[
Bertl: please check dm when you get time
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