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| 00:48 | siddhantsahu | Which white balancing algorithm is being used in the AXIOM Beta?
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| 04:48 | johnathan | Hi all, wondering if its possible to change the resolution of the HDMI output easily? What are the scn_reg 32-35 values in gen_init.sh / how to get them from a standard modeline? assuming its possible?
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| 05:04 | Bertl_oO | Hey johnathan!
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| 05:05 | Bertl_oO | To some degree it is possible to adjust the HDMI output but you have to adjust the memory readers as well
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| 05:06 | Bertl_oO | the first step is to figure out the parameters for your new resolution, like clock frequency, total and sync width/height as well as front/back porch
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| 06:24 | johnathan | the resolution is 1280x800, 83.5 MHz pixel clock, 49.68 KHz horizontal, 60 hz vertical, 1680 pixels per line, 831 lines per frame, 1280 active pixels per line, 800 active pixels per frame, 323 first pixel position, 22 first active line, positive hysnc/vsync
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| 06:25 | johnathan | my goal is to just be able to display a static image with the utility out the hdmi (no live preview)
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| 07:11 | se6astian | johnathan: that sounds technically possible definitely
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| 07:13 | se6astian | siddhantsahu: 01:48:06> Which white balancing algorithm is being used in the AXIOM Beta? <- there is no whitebalancing currently but you can use a color matrix to balance the different color channels
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| 07:17 | siddhantsahu | Ok. Will automatic white balancing algorithm useful for AXIOM Beta?
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| 07:21 | Bertl_oO | johnathan: the clock will be the most problematic in your case
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| 07:21 | se6astian | siddhantsahu: I think so yes
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| 07:21 | se6astian | for preview purposes definitely
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| 07:21 | se6astian | in the intended raw recording the channels will be stored without matrix/wb applied
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| 07:22 | siddhantsahu | Ok then looking forward to build it.
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| 07:22 | se6astian | great
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| 07:23 | Bertl_oO | johnathan: in theory you can change the PLL values on the fly, but it is rather tricky, so you're probably better of either going with the available clocks or rebuilding the FPGA bitstream with your specific clock
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| 07:23 | siddhantsahu | Yes I understand that the raw recorded values will be stored without any wb applied.
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| 07:24 | siddhantsahu | Yes, for preview it might be helpful.
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| 12:07 | johnathan | I think I might be able to get away with keeping the clock the same, but how do I figure out the other values in gen_init.sh? the 32-35 scn_reg values?
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| 12:09 | johnathan | also are there instructions on building and experimenting with the fpga fabrics (stuff under peripherals)? I have everything else building and able to make changes as needed except that stuff, there doesn't appear to be any build scripts/makefiles?
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| 12:12 | BAndiT1983 | jonathan, fabrics are there as pre-compiled units
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| 12:13 | BAndiT1983 | switch the branch to fullstack to get also vhd files
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| 12:14 | BAndiT1983 | oops, i mean johnathan
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| 12:55 | se6astian | BAndiT1983: I just checked our firmware repo and noticed that all VHDL sources have been removed
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| 12:56 | se6astian | did we decide to exclude them there?
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| 12:56 | se6astian | the fullstack branch is actually different hardware
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| 12:56 | BAndiT1983 | don't know, but aren't VHD files in the fullstack branch the sources?
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| 12:57 | se6astian | yes they are but as I said for a different hardware
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| 12:57 | se6astian | they were forked from our original sources
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| 12:57 | BAndiT1983 | ah, ok, am not that deep in the FPGA topic
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| 12:57 | BAndiT1983 | and in peripherals?
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| 12:59 | se6astian | we should be able to bring the files back from the github history
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| 13:00 | se6astian | ah wait its all there
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| 13:00 | se6astian | in peripherals indeed
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| 13:00 | se6astian | https://github.com/apertus-open-source-cinema/axiom-beta-firmware/tree/master/peripherals/soc_main
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| 13:01 | BAndiT1983 | off for now, will be back later
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| 15:27 | Bertl_oO | johnathan: 32 is the start of the video preamble, 33 the start of the video guard band, 34 the end of the TERC4 coding and 35 is the end of the guard band
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| 16:46 | se6astian | johnathan: since you are kind of exploring uncharted territory here it would be great if you could start by updating/extending the wiki documentation about this
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| 21:57 | anuejn | jonathan: they are not automatically build indeed
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| 21:58 | anuejn | this is mostly du to licensing issues with vivado
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| 22:01 | anuejn | however if you install vivado, you should be able to build the gateware using the tcl script in the main_soc folder
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| 22:01 | johnathan | I think I've figured out how to translate the modeline I need and going to attempt a build with the new clock
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| 22:02 | anuejn | (ht might not meet timing on first pnr try, ask bertl for details)
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| 22:02 | anuejn | jonethan: nice :)
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| 22:06 | johnathan | it looks to be set to HDMI_160, what reference (how to get the DIVIDE and MULT_F?)
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| 22:10 | anuejn | ask Bertl ;)
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| 22:10 | anuejn | good night everyone!
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| 22:26 | RexOrCine | (18:46:30) se6astian: johnathan: since you are kind of exploring uncharted territory here it would be great if you could start by updating/extending the wiki documentation about this < Can you guide him to where it should go, or start a new page in the interim if needs be (while any data is compiled).
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| 22:29 | johnathan | yes assuming I'm successful I'll make a guide for how to get other hdmi output devices working :)
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| 22:32 | RexOrCine | Good man. Might be best to start a new page while you edit and revisit, and link us, then we can catalogue any works in the appropriate place once more complete. Up to you though, there'll be a spot in the manual for this but it'll mean you'd need to keep scrolling to the right spot possibly.
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| 22:48 | RexOrCine | ... or do it locally.
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