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| 00:02 | Bertl_oO | off to bed now ... have a good one everyone!
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| 06:41 | Bertl | morning folks!
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| 06:54 | Bertl | off for now ... bbl
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| 12:08 | se6astian | good day
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| 12:29 | intracube | afternoon :)
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| 12:51 | se6astian | first 3d print tests of simple enclosure
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| 12:51 | se6astian | https://twitter.com/ApertusOSCinema/status/693426610301698048
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| 14:03 | intracube | se6astian: this is experimental right?
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| 14:03 | intracube | beta cases will still be cnc milled?
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| 14:04 | intracube | nvm
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| 14:04 | intracube | has just read the roadmap
| | 15:07 | se6astian | :)
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| 15:08 | se6astian | more details in next teamtalk
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| 15:08 | se6astian | we already have a full enclosure design in CAD
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| 15:08 | se6astian | gotta go
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| 15:42 | jjshawver_ | hey Bertl
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| 15:42 | jjshawver_ | do you guys have any documentation anywhere on getting started with the FPGA stuff you have?
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| 15:42 | jjshawver_ | found the git repo, but it's a flat hierarchy without test benches that I noticed
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| 15:46 | Bertl_oO | changed nick to: Bertl
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| 15:46 | Bertl | hey jjshawver_!
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| 15:47 | Bertl | the most recent source can be found here: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/cmv_hdmi3/
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| 15:47 | Bertl | still there is no documentation or test benches, because when the software was developed (for the alpha) there was not much time for that
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| 15:48 | jjshawver_ | that makes sense.
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| 15:48 | jjshawver_ | any starting projects?
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| 15:48 | Bertl | well, basically the entire firmware needs an overhaul/rewrite
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| 15:49 | jjshawver_ | gotcha. probably a good time to swap to automake and the git repo?
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| 15:49 | Bertl | there are a bunch of ideas (what we learned from the current version)
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| 15:49 | jjshawver_ | very cool
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| 15:50 | Bertl | yes, no problem with that, although I don't see how automake would help much, but please elaborate ...
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| 15:50 | jjshawver_ | just nice for bundling things. especially if you utilize makefiles
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| 15:50 | jjshawver_ | assuming your firmware was more than vhdl. probably c, or a linux environment etc
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| 15:51 | jjshawver_ | automake can handle the dependecies and get you an initial setup so that people can get started really easily
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| 15:51 | Bertl | ah, you are talking different parts, not just the firmware blob
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| 15:51 | jjshawver_ | aka, with automake you can create rpms, deb files etc
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| 15:51 | Bertl | yes, I'm aware of the automake capabilities
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| 15:52 | Bertl | anyway, as I said, no problem with that
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| 15:52 | Bertl | I can check in the latest version (if I haven't already) to github
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| 15:52 | jjshawver_ | ok cool. is the firmware somewhere else then?
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| 15:52 | Bertl | let me check
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| 15:53 | Bertl | ah, https://github.com/apertus-open-source-cinema/beta-software/tree/master/cmv_hdmi3 seems to be "up-to-date"
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| 15:54 | Bertl | so you can use that to work with (regarding firmware)
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| 15:54 | jjshawver_ | ok cool. does vivado dump out a block diagram or anything like that?
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| 15:54 | jjshawver_ | looking for an overall idea of what's going on first, and then to dive in at the block level as needed
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| 15:55 | Bertl | there are options for schematic and similar in vivado, but as the cmv_hdmi3 does not work at the "IP" level but on the "VHDL" level I don't think there is anything useable
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| 15:55 | Bertl | but I can give you a quick rundown what does what
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| 15:56 | jjshawver_ | yeah. I wasn't really meaning "schematic capture"
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| 15:56 | jjshawver_ | more so just the top level documentation
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| 15:56 | jjshawver_ | verdi (an expensive tool) generates one for you from the HDL code you use.
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| 15:57 | Bertl | yeah, well, we don't use expensive tools, all free (speech kind preferred :)
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| 15:57 | jjshawver_ | the dvt plugin for eclipse looks pretty nice as well. although that can also be rather spendy 700 per seat
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| 15:57 | Bertl | https://wiki.apertus.org/index.php/AXIOM_Alpha_Software
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| 15:57 | jjshawver_ | makes sense
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| 15:58 | Bertl | there you can find the Pipelines
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| 15:58 | Bertl | basically the firmware works in two almost independant parts
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| 15:58 | jjshawver_ | ok cool. that's a good start
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| 15:58 | jjshawver_ | are all of the vhdl files shown at this level?
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| 15:59 | jjshawver_ | assuming there's more
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| 15:59 | Bertl | an input pipeline which receives the images from the sensor, rearranges the data and bursts it into memory
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| 15:59 | Bertl | and an output pipeline which fetches the data from memory, combines and formats it and then outputs the data via HDMI
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| 16:00 | jjshawver_ | ok. so a specific hardware DMA type of setup
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| 16:00 | jjshawver_ | dual port DRAM i take it?
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| 16:00 | jjshawver_ | or are you using a different type of memory?
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| 16:00 | Bertl | back then, on the Alpha we used a dedicated HDMI chip, on the Beta we do the HDMI output in the FPGA
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| 16:00 | Bertl | we are using the DDR memory on the Microzed
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| 16:00 | jjshawver_ | ok cool. that makes sense
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| 16:01 | Bertl | and the PL <-> DDR transfer happens via the AXI busses
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| 16:01 | jjshawver_ | not sure if you guys are interested this late in the game, but I did hear about an alternate platform you might like
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| 16:01 | jjshawver_ | https://www.crowdsupply.com/krtkl/snickerdoodle
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| 16:01 | jjshawver_ | same xilinx chip I believe
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| 16:02 | Bertl | hehe, we are backer of the snickerdoodle :)
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| 16:02 | jjshawver_ | just 55 a pop instead of the 250
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| 16:02 | jjshawver_ | nice :)
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| 16:02 | Bertl | so, we have been looking at that and other alternatives for some time
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| 16:02 | jjshawver_ | any thoughts on the other alternatives?
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| 16:03 | Bertl | the thing is, with an 1000 USD sensor, the 200 USD for the Microzed are not _that_ much
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| 16:04 | jjshawver_ | that is fair, although any savings can be nice
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| 16:04 | jjshawver_ | any formal pin locations for shields yet?
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| 16:05 | Bertl | we have been investigating the parallella, which would be a nice option for low end sensors
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| 16:05 | jjshawver_ | meaning something as formal as the Arduino where you can infinitely stack them
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| 16:05 | jjshawver_ | yeah. the parallella is a very cool board. guessing you'd go the embedded flavor for the more GPIO
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| 16:05 | Bertl | we also have been investigating the Picozed, which is a stripped down version of the Microzed
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| 16:06 | jjshawver_ | that definitely could be nice
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| 16:06 | Bertl | anyway, for the current Beta the Microzed interface has been chosen/fixed, but that doesn't mean that a future version won't use a different devel board
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| 16:07 | jjshawver_ | most definitely. that's part of the fun with the open source aspect. any dev board can be plugged in later
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| 16:08 | Bertl | so, for the FPGA part, would you like a walk through?
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| 16:08 | jjshawver_ | that would be great, although some solid documentation would probably help more so.
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| 16:09 | jjshawver_ | I do know how time puts that aside
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| 16:09 | Bertl | you have to write that or use the source :)
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| 16:09 | jjshawver_ | works for me
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| 16:09 | jjshawver_ | latex cool with you guys?
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| 16:09 | Bertl | definitely
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| 16:09 | jjshawver_ | documentation isn't a favorite, but definitely helps. so I can start to chip away there initially
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| 16:11 | jjshawver_ | and if you guys are doing a rehaul, would you potentially be interested in swapping to SystemVerilog instead?
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| 16:11 | jjshawver_ | removes the need of a lot of verbose coding
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| 16:12 | jjshawver_ | aka, wiring modules up shrinks to just a couple lines of code
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| 16:14 | Bertl | personally I'm not a fan of Verilog per se but I'm not against it if you can make a point
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| 16:14 | Bertl | note that recent Vivado support VHDL 2009 (at least most of it) so VHDL has become a lot more attractive than before
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| 16:15 | jjshawver_ | I'm not familiar with VHDL 2009. Currently using SystemVerilog 2012. Which I think Vivado also supports
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| 16:15 | jjshawver_ | I'd agree that VHDL has some serious advantages over Verilog 2001. Although SystemVerilog simplifies things quite a bit
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| 16:15 | Bertl | 2012 you say, you should probably check that, xilinx is not so fast in picking up new standards :)
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| 16:17 | Bertl | note that a main goal is to create code which can be rebuilt without a special license or expensive toolchain
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| 16:17 | Bertl | i.e. whatever we do, we are limited to the Web Pack provided by Xilinx
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| 16:18 | jjshawver_ | that's a good goal. I'm pretty sure that I read somewhere that Vivado supported it all. Although there are Testbench specific things in the language that you can't synthesize with.
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| 16:19 | jjshawver_ | Trying to find where I read that
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| 16:19 | jjshawver_ | but yeah. SystemVerilog has interfaces, which are very similar to bundled cables that are plug and play between modules
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| 16:19 | jjshawver_ | it also has enums, typedefs, structs and unions
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| 16:20 | jjshawver_ | so moving data between modules can be read and deciphered rather easily. plus, bit width changes don't effect you nearly as much
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| 16:20 | Bertl | in any case it should be combineable with VHDL, so as I said, if you can make a point, that's fine with me
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| 16:21 | Bertl | note that there are also quite nice alternatives (wrappers) for VHDL, like MyHDL
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| 16:21 | jjshawver_ | also has keywords to help protect synthesis. i.e. always_comb will throw warnings if there are inferred latches, and always_ff is a good way of showing when registers are being used
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| 16:22 | jjshawver_ | hmm.. haven't heard of MyHDL. does vivado support those?
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| 16:22 | Bertl | it's open source software, and Vivado starts at the VHDL/Verilog level
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| 16:23 | Bertl | anyway, plenty of options :)
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| 16:24 | jjshawver_ | most definitely. I'll have to check out MyHDL and see what is nice about it. (as I'm sure you've noticed, I'm partial to SystemVerilog - primarily to it's C similarities)
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| 16:24 | jjshawver_ | But definitely good to try something new :)
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| 16:25 | Bertl | when I started coding HDL (which was when we started with the Alpha design :) I checked out both languages
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| 16:25 | Bertl | and then decided to go for the more structured and well defined one instead of the the one which was more familiar :)
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| 16:26 | jjshawver_ | I'd consider SystemVerilog almost as a third language. A blend between VHDL, Verilog, C and a little of its own :)
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| 16:26 | Bertl | note that SystemVerilog is a huge improvement over Verilog
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| 16:26 | jjshawver_ | most definitely agree that SystemVerilog is a huge improvement over verilog.
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| 16:27 | Bertl | so I'd say: make yourself familiar with e.g. the input pipeline
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| 16:27 | Bertl | check out what the Web Pack provides in this regard
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| 16:28 | Bertl | and e.g. rewrite part of it in SystemVerilog to show how that improves the design
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| 16:28 | Bertl | or let me know what you want to work on ...
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| 16:29 | jjshawver_ | sounds good to me! :) That's definitely a good starting point. I'll probably have to badger you at some points to get a thorough understanding of the layout from time to time
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| 16:29 | jjshawver_ | what hours are you typically available?
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| 16:29 | Bertl | no problem, I'm usually around and definitely answer any questions directed at my nick at some point
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| 16:31 | jjshawver_ | ok. sounds good. thanks!
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| 16:31 | Bertl | hard to say, but usually my hours are very similar to the US timezones
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| 16:31 | jjshawver_ | I'll go ahead and get started and get back to you periodically in the next couple weeks
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| 16:32 | jjshawver_ | would you prefer I fork the git repo or work right out of master? (probably would need to be added to the repo for that)
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| 16:33 | Bertl | shouldn't be a problem to get you added to the repo, but I guess for a start it's simpler to fork
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| 16:33 | jjshawver_ | works for me! thanks
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| 19:18 | Phrk_ | Hello, is someone here using a editor on linux in a "pro" way ?
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| 19:18 | Bertl | not sure what that even means :) I'm using vim in a "pro" way :)
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| 19:19 | Phrk_ | Vim is a very serious pro software
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| 19:19 | Phrk_ | not marketing bullshit, i mean pro like you can do a lot of thing with
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| 19:20 | Bertl | correct, so is emacs
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| 19:20 | Phrk_ | like 4:2:2 or 4:4:4 10bit support
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| 19:20 | Bertl | ah, so the question is regarding film editing
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| 19:20 | Phrk_ | by editor, i mean video editor (sorry)
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| 19:20 | Phrk_ | ye
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| 19:21 | Phrk_ | I'm currently using vegas on windows, but i want to slowly change my workflow on linux, if it's possible
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| 19:22 | Bertl | I see, well, I'm the wrong person for that question then, I don't do video editing ...
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| 19:22 | Phrk_ | :'(
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| 19:25 | Bertl | but there are a number of other folks around (or better sometimes around) who do
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| 19:25 | Bertl | so give it a little time and maybe ask again if you don't get feedback
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| 19:26 | Phrk_ | ok
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| 20:40 | alexML | for those of you interested in PLR: you may want to check my first notes here: https://wiki.apertus.org/index.php/PLR
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| 20:46 | Bertl | nice, tx!
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| 20:49 | alexML | that was just scratching the surface :P
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| 20:49 | alexML | I wonder if that nonlinear highlight response from regular exposures (that "nondata" part) may be actually a side effect of the PLR circuits
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| 20:50 | Bertl | possible
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| 20:53 | Bertl | off for a nap ... bbl
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| 20:53 | Bertl | changed nick to: Bertl_zZ
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