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#apertus IRC Channel Logs

2017/12/28

Timezone: UTC


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BAndiT1983|away
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BAndiT1983
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12:35
anuejn
davidak: do you know, where the betas are?
12:37
anuejn
we want to test a new image iteration...
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BAndiT1983|away
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19:28
felix_
the sdi adapter cables that i ordered from digikey aren't really mechanically compatible with the 3d-printed cable holders :/
20:02
Bertl_oO
how's that?
20:04
RexOrCine
Very unsure about what's happening at CCC.
20:04
RexOrCine
There's been no mention of Beta across socials at this point.
20:06
RexOrCine
And links to any video would be great.
20:17
felix_
Bertl_oO: bei den neuen kabeln ist das metallstueck hinten um das kabel laenger, weshalb das mit dem plastikstueck, was an der stelle vom kabelbinder zwischen kabel und der platte ist, etwas kollidiert. der stecker trifft so nicht senkrecht auf die buchse, weshalb ich das kabel da nicht angeschlossen bekomme
20:19
Bertl_oO
I see ... well, you have two cables which work, so that should not be a problem for now and I'm sure se6astian can adapt the design ...
20:20
felix_
yes, that's not a big problem
20:21
felix_
RexOrCine: yesterday i wasn't at the apertus table, because i would habe been the only one for quite some time; went to the openfpga table and reviewed and wrote some coreboot patches
20:23
felix_
iirc david wanted to film some footage
20:25
RexOrCine
If you see him could you please tell him that if he captures any event photos to copy in @AXIOM_Community on Twitter or to send them to team@apertus.org if poss.
21:09
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21:24
BAndiT1983
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21:51
davidak[m]
felix_: we want to connect the beta to the VOC render cube via SDI now. do you want to come?
21:55
felix_
have you seen florent today? i think he's the only one who really knows how to get that running at the moment
21:59
felix_
well and herbert knows how to talk to the module from the zynq side, but i'm not sure if we ever tested that
22:00
felix_
should i go to the apertus assembly now anyway?
22:01
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22:01
Bertl_oO
the serial connection from the zynq was tested (not with the SDI firmware, but with a loopback)
22:02
Bertl_oO
and one of the three modules you have should still have the serial cables attached
22:15
Bertl_oO
so what I'm saying is that it should only depend on the SDI module firmware not the Beta ...
22:21
davidak[m]
felix_: tim said florent went home for today
22:26
davidak[m]
you can come and help figure things out and see the setup when it works
22:26
davidak[m]
we have connected the camera and powered it up, but they get no output from SDI
22:27
davidak[m]
do i still have to start the kick script?
22:35
felix_
you need to load the bitstream into the sdi module, run some init script on the camera and then send some command to the sdi module
22:36
felix_
i'll go to the apertus assembly soon
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23:15
felix_
Bertl_oO: on which uart on the zynq is the srial port of the sdi module?
23:19
Bertl_oO
ttyS1
23:19
_florent_
felix_: i'm no longer at the venue but can try to help
23:19
Bertl_oO
*ttyPS1
23:20
_florent_
felix_: do you have the bitstream?
23:24
felix_
i flashed the second bitstream you emailed
23:28
_florent_
ok, is it working?
23:36
felix_
not really
23:38
Bertl_oO
but it wasn't working at Vienna either
23:38
Bertl_oO
(with the unmodified setup)
23:40
felix_
we did get a video stream via sdi in vienna
23:41
anuejn
Bertl: im currently working on the images for the beta...
23:41
anuejn
but somehow everything hangs, when we are executing the kick.sh script
23:42
anuejn
just when it tries to write to address 0x60000144
23:42
anuejn
any ideas?
23:42
Bertl_oO
where do you test it?
23:43
anuejn
and is there any way to check, wether the fpga bitstream is loaded properly?
23:43
anuejn
i testes it with one of the betas at congress...
23:44
Bertl_oO
so you are testing your image on those betas?
23:45
anuejn
yes.
23:45
anuejn
(the one thats currently not involved in the sdi experiments)
23:45
Bertl_oO
okay, good
23:46
Bertl_oO
well, a write (or read) to 0x6xxxxxxx will hang if there is no AXI slave present
23:46
Bertl_oO
which in turn means, that the FPGA bitstream was not loaded or is not the correct one
23:47
anuejn
yeah that could be entirely true...
23:47
anuejn
i only have amba in the devicetree
23:47
anuejn
*not devicetree unde /sys/
23:48
Bertl_oO
the devicetree doesn't matter
23:48
anuejn
yeah sorry
23:48
Bertl_oO
and the AXI is part of AMBA
23:48
anuejn
is there any easy way to check, wether the bitstream is loaded?
23:49
anuejn
but the paths vary quite a lot between what the scripts asume and what is present in my /sys
23:49
Bertl_oO
yes, when a bitstream is loaded correctly, the DONE flag/pin will be set
23:50
anuejn
where can i find it?
23:50
Bertl_oO
the pin is connected to the blue LED on the microzed, but we override that in our bitstream to use the LED for indicating a frame capture
23:51
Bertl_oO
but you can read the flag from the devcfg registers
23:53
Bertl_oO
devcfg.STATUS bit 2 and 4
23:53
BAndiT1983|away
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23:54
BAndiT1983
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23:55
Bertl_oO
and if the devcfg driver is loaded (Linux) you can use /sys/devices/soc0/amba/f8007000.devcfg/prog_done
23:55
Bertl_oO
(or wherever f8007000.devcfg is in your tree)
23:56
anuejn
this bit is set
23:57
anuejn
i loaded http://vserver.13thfloor.at/Stuff/AXIOM/BETA/cmv_hdmi3_dual_30.bit bitstream