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| 05:13 | Bertl_oO | off to bed now ... have a good one everyone!
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| 08:53 | se6astian | good day
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| 13:35 | Bertl | morning folks!
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| 16:26 | comradekingu | Bertl: I snoozed, so it counts. Good morning
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| 16:27 | comradekingu | mithro: I can help editing the manual into a nofluff-state
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| 16:30 | comradekingu | se6astian Would feet like this do? https://ixquick-proxy.com/do/spg/show_picture.pl?l=english&rais=1&oiu=https%3A%2F%2Fwww.native-instruments.com%2Fforum%2Fattachments%2Fimg_2417-jpg.49233%2F&sp=1d1bc228d3c75c71a91bbafb559a057e
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| 16:33 | comradekingu | My native instruments - audio kontrol 1 has black square ones
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| 16:33 | comradekingu | If one does helical cuts they could be o-rings
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| 16:36 | se6astian | looks huge
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| 16:36 | se6astian | what are the dimensions?
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| 16:52 | comradekingu | Only a few mm high, hold on
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| 16:59 | comradekingu | 2 cm x 1.4cm x 0,35 cm
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| 16:59 | comradekingu | Cut into a longitudal groove and fastened with one screw
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| 17:58 | se6astian | team meeting starting in 2 minutes
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| 18:00 | se6astian | meeting time!
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| 18:01 | se6astian | in the usual habbit please pm me now if you want to report anything
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| 18:02 | se6astian | ok this will be a quick meeting
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| 18:02 | se6astian | only Bertl :)
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| 18:02 | se6astian | please go ahaead
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| 18:02 | Bertl | okay, then
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| 18:03 | Bertl | I've spent the last few weeks with several tests and investigations and building test hardware for future development
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| 18:03 | Bertl | on the software side, I did investigate recent Vivado HLS and the applicability to AXIOM firmware
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| 18:04 | Bertl | the first tests there seem promising and might speed up firmware development and modifications dramatically
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| 18:04 | Bertl | it's not all simple and problem free, but it doesn't look bad either
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| 18:05 | Bertl | I also did a bunch of tests with the TE0714 boards and their gigabit tranceivers
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| 18:05 | se6astian | vivado HLS means you can write fpga code in C/C++ like syntax right?
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| 18:06 | Bertl | yep High Level Synthesis
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| 18:06 | Bertl | specifically we designed a setup where two TE0714 communicate over 5" OSHpark PCB with different pair configurations
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| 18:06 | Bertl | and extensive IBERT testing showed that 3Gbps is absolutely no problem and 6Gbps can be achieved with some fine tuning
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| 18:07 | felix_ | last time i tried (2013), vivado hls didn't generate very good or efficient code :/
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| 18:08 | Bertl | BER for 5Gbps over 5" PCB plugged into PCIe x1 on each end, routed over 1" PCB to razor beam connectors where the TE0714 are attached was lower than 1E-13
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| 18:08 | Bertl | felix_: yes, a lot has improved and while certain parts still need to be coded in HDL, it does a pretty good job on the interface side
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| 18:08 | felix_ | ok, nice
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| 18:09 | Bertl | integration is a lot smoother than it was in the beginning
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| 18:10 | Bertl | on the AXIOM side itself, I'm working on the second generation SFE Testing hardware (v0.2) which uses an aray of 15 PIC microcontroller to verify SFE functionality
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| 18:10 | Bertl | I also built the first test hardware for our future eMMC plugin module
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| 18:11 | Bertl | and some preliminary tests on the Smart Power Adapter were done, but the firmware is still in a very early stage
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| 18:11 | Bertl | besides that, GSoC final evaluation is coming up, so a lot of time was spent on mentoring as well
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| 18:12 | Bertl | that's basically it form my side ...
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| 18:12 | felix_ | is currently reading through all the paperwork from the ministry of education and research and will travel to berlin on the day after tomorrow for the prototype fund kick-off-event
| | 18:13 | felix_ | from next month on i'll work first on the sdi project and then on the axi integration for migen/litex
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| 18:15 | felix_ | the plan is to have an AXIOM beta with sdi output module for the streaming of the 34c3; at least that would be a really nice showcase
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| 18:16 | se6astian | thanks Bertl
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| 18:16 | se6astian | felix_: does that mean the grant has officially been approved now?
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| 18:16 | felix_ | oh and we are currently looking for another name foer the sdi subproject, since lite sdi is already used for a product with sdi interface
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| 18:17 | se6astian | "open sdi"?
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| 18:17 | Bertl | I still would suggest to contact them if they actually mind us using a very similar name
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| 18:18 | felix_ | se6astian: i got that letter maybe a month ago, but didn't have time and energy until now to read through all the officialese
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| 18:18 | Bertl | (because if they don't, it's a moot point)
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| 18:18 | se6astian | quick report from my side: max is currently moving and therefore has trouble finishing the upcoming TT 13.1 (rough edit is done)
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| 18:18 | felix_ | so yeah, that's officially approved
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| 18:19 | se6astian | ah great!
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| 18:19 | se6astian | as soon as he settled in and unpacked his editing suit we should have the next episode ready
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| 18:22 | se6astian | and I am slowly catching up with all things to push forward and getting in touch with all the people to get things rolling again on all fronts after returning from vacation
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| 18:22 | se6astian | good progress was made with Full Enclosure CAD rework
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| 18:22 | se6astian | and we are tuning the PnP machine again right now
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| 18:23 | se6astian | if there are no further points/comments I would conclude todays meeting
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| 18:23 | se6astian | next meeting in 2 weeks as usual
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| 18:24 | comradekingu | Maybe the 34c3 cam can be my paid for camera, since im going there?
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| 18:24 | comradekingu | yeeeees
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| 18:24 | se6astian | :)
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| 18:25 | se6astian | lets discuss that when the date approaches
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| 18:25 | se6astian | but it would be a possibility
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| 18:26 | se6astian | meeting minutes updated
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| 18:26 | se6astian | https://wiki.apertus.org/index.php/IRC_Team_Meeting_2017-08-28
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| 18:27 | felix_ | se6astian: no, the grant is not for the sdi *module*, but for the gateware and firmware
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| 18:27 | felix_ | the prototype fund is not for hardware development
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| 18:27 | felix_ | that's quite important...
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| 18:28 | se6astian | "Felix shared the news that the grant to work on gateware and firmware of an AXIOM Beta SDI 6G module has been officially approved" ?
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| 18:28 | comradekingu | what is gateware?
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| 18:28 | felix_ | gateware == fpga design
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| 18:28 | felix_ | se6astian: yep
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| 18:29 | comradekingu | ok
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| 18:29 | comradekingu | ty
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| 18:29 | comradekingu | I am now wellaware
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| 18:52 | se6astian | good and bad news from the pnp front
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| 18:53 | se6astian | good news: we again got the issues sorted to achieve perfect accuracy placements
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| 18:53 | se6astian | bad news: we now know the z axis position encoder has a hardware issue which explains why we just crashed the nozzle into the bottom vision camera and pierced the glass
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| 19:01 | Bertl | nice :/
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| 19:10 | Bertl | off for now ... bbl
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| 19:51 | se6astian | off too
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| 22:01 | comradekingu | https://www.crowdsupply.com/rhs-research/nanoevb?utm_source=FPGA+Enthusiasts&utm_campaign=0a0faf3660-EMAIL_CAMPAIGN_2017_06_20&utm_medium=email&utm_term=0_9b7b9ea11f-0a0faf3660-112464177
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