Current Server Time: 15:43 (Central Europe)

#apertus IRC Channel Logs

2017/08/28

Timezone: UTC


01:28
XDjackieXD
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04:13
Bertl_oO
off to bed now ... have a good one everyone!
04:13
Bertl_oO
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bertl_zZ
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se6astian|away
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07:53
se6astian
good day
07:54
niculescu_vlad|a
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niculescu_vlad
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niculescu_vlad|a
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Spirit532_
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niculescu_vlad
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niculescu_vlad|a
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12:35
Bertl_zZ
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12:35
Bertl
morning folks!
12:51
niculescu_vlad
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illwieckz_
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BAndiT1983|away
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jucar
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15:26
comradekingu
Bertl: I snoozed, so it counts. Good morning
15:27
comradekingu
mithro: I can help editing the manual into a nofluff-state
15:30
comradekingu
se6astian Would feet like this do? https://ixquick-proxy.com/do/spg/show_picture.pl?l=english&rais=1&oiu=https%3A%2F%2Fwww.native-instruments.com%2Fforum%2Fattachments%2Fimg_2417-jpg.49233%2F&sp=1d1bc228d3c75c71a91bbafb559a057e
15:33
comradekingu
My native instruments - audio kontrol 1 has black square ones
15:33
comradekingu
If one does helical cuts they could be o-rings
15:36
se6astian
looks huge
15:36
se6astian
what are the dimensions?
15:51
jucar
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BAndiT1983
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15:52
comradekingu
Only a few mm high, hold on
15:59
comradekingu
2 cm x 1.4cm x 0,35 cm
15:59
comradekingu
Cut into a longitudal groove and fastened with one screw
16:07
BAndiT1983|away
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illwieckz
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BAndiT1983
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illwieckz
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aombk
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sebix
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16:58
se6astian
team meeting starting in 2 minutes
17:00
se6astian
meeting time!
17:01
se6astian
in the usual habbit please pm me now if you want to report anything
17:02
se6astian
ok this will be a quick meeting
17:02
se6astian
only Bertl :)
17:02
se6astian
please go ahaead
17:02
Bertl
okay, then
17:03
Bertl
I've spent the last few weeks with several tests and investigations and building test hardware for future development
17:03
Bertl
on the software side, I did investigate recent Vivado HLS and the applicability to AXIOM firmware
17:04
Bertl
the first tests there seem promising and might speed up firmware development and modifications dramatically
17:04
Bertl
it's not all simple and problem free, but it doesn't look bad either
17:05
Bertl
I also did a bunch of tests with the TE0714 boards and their gigabit tranceivers
17:05
se6astian
vivado HLS means you can write fpga code in C/C++ like syntax right?
17:06
Bertl
yep High Level Synthesis
17:06
Bertl
specifically we designed a setup where two TE0714 communicate over 5" OSHpark PCB with different pair configurations
17:06
Bertl
and extensive IBERT testing showed that 3Gbps is absolutely no problem and 6Gbps can be achieved with some fine tuning
17:07
felix_
last time i tried (2013), vivado hls didn't generate very good or efficient code :/
17:08
Bertl
BER for 5Gbps over 5" PCB plugged into PCIe x1 on each end, routed over 1" PCB to razor beam connectors where the TE0714 are attached was lower than 1E-13
17:08
Bertl
felix_: yes, a lot has improved and while certain parts still need to be coded in HDL, it does a pretty good job on the interface side
17:08
felix_
ok, nice
17:09
Bertl
integration is a lot smoother than it was in the beginning
17:10
Bertl
on the AXIOM side itself, I'm working on the second generation SFE Testing hardware (v0.2) which uses an aray of 15 PIC microcontroller to verify SFE functionality
17:10
Bertl
I also built the first test hardware for our future eMMC plugin module
17:11
Bertl
and some preliminary tests on the Smart Power Adapter were done, but the firmware is still in a very early stage
17:11
Bertl
besides that, GSoC final evaluation is coming up, so a lot of time was spent on mentoring as well
17:12
Bertl
that's basically it form my side ...
17:12
felix_
is currently reading through all the paperwork from the ministry of education and research and will travel to berlin on the day after tomorrow for the prototype fund kick-off-event
17:13
felix_
from next month on i'll work first on the sdi project and then on the axi integration for migen/litex
17:15
felix_
the plan is to have an AXIOM beta with sdi output module for the streaming of the 34c3; at least that would be a really nice showcase
17:16
se6astian
thanks Bertl
17:16
se6astian
felix_: does that mean the grant has officially been approved now?
17:16
felix_
oh and we are currently looking for another name foer the sdi subproject, since lite sdi is already used for a product with sdi interface
17:17
se6astian
"open sdi"?
17:17
Bertl
I still would suggest to contact them if they actually mind us using a very similar name
17:18
felix_
se6astian: i got that letter maybe a month ago, but didn't have time and energy until now to read through all the officialese
17:18
Bertl
(because if they don't, it's a moot point)
17:18
se6astian
quick report from my side: max is currently moving and therefore has trouble finishing the upcoming TT 13.1 (rough edit is done)
17:18
felix_
so yeah, that's officially approved
17:19
se6astian
ah great!
17:19
se6astian
as soon as he settled in and unpacked his editing suit we should have the next episode ready
17:22
se6astian
and I am slowly catching up with all things to push forward and getting in touch with all the people to get things rolling again on all fronts after returning from vacation
17:22
se6astian
good progress was made with Full Enclosure CAD rework
17:22
se6astian
and we are tuning the PnP machine again right now
17:23
se6astian
if there are no further points/comments I would conclude todays meeting
17:23
se6astian
next meeting in 2 weeks as usual
17:24
comradekingu
Maybe the 34c3 cam can be my paid for camera, since im going there?
17:24
comradekingu
yeeeees
17:24
se6astian
:)
17:25
se6astian
lets discuss that when the date approaches
17:25
se6astian
but it would be a possibility
17:26
se6astian
meeting minutes updated
17:26
se6astian
https://wiki.apertus.org/index.php/IRC_Team_Meeting_2017-08-28
17:27
felix_
se6astian: no, the grant is not for the sdi *module*, but for the gateware and firmware
17:27
felix_
the prototype fund is not for hardware development
17:27
felix_
that's quite important...
17:28
se6astian
"Felix shared the news that the grant to work on gateware and firmware of an AXIOM Beta SDI 6G module has been officially approved" ?
17:28
comradekingu
what is gateware?
17:28
felix_
gateware == fpga design
17:28
felix_
se6astian: yep
17:29
comradekingu
ok
17:29
comradekingu
ty
17:29
comradekingu
I am now wellaware
17:37
niculescu_vlad|a
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17:48
slikdigit
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17:52
se6astian
good and bad news from the pnp front
17:53
se6astian
good news: we again got the issues sorted to achieve perfect accuracy placements
17:53
se6astian
bad news: we now know the z axis position encoder has a hardware issue which explains why we just crashed the nozzle into the bottom vision camera and pierced the glass
18:01
Bertl
nice :/
18:10
Bertl
off for now ... bbl
18:10
Bertl
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18:51
se6astian
off too
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se6astian
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20:28
BAndiT1983|away
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se6astian|away
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BAndiT1983
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BAndiT1983|away
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21:01
comradekingu
https://www.crowdsupply.com/rhs-research/nanoevb?utm_source=FPGA+Enthusiasts&utm_campaign=0a0faf3660-EMAIL_CAMPAIGN_2017_06_20&utm_medium=email&utm_term=0_9b7b9ea11f-0a0faf3660-112464177
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BAndiT1983
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se6astian
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niculescu_vlad
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illwieckz
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niculescu_vlad|a
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niculescu_vlad
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