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#apertus IRC Channel Logs

2019/05/28

Timezone: UTC


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RexOrCine
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BAndiT1983|away
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Bertl_zZ
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06:59
Bertl
morning folks!
06:59
apurvanandan[m]
Good morning!
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BAndiT1983
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sebix
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se6astian|away
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se6astian
good day
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Dev_
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09:26
Dev_
Hello Bandit1983 , sorry I wasn't able to attend the yesterday's meeting , could u able to check my email . Any feedback ??
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Dev_
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09:28
Bertl
off for now ... bbl
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Bertl
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BAndiT1983
hi Dev_, i've replied to your email yesterday already, please check your spam folder, as Supragya retrieved it from his
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sebix
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Bertl_oO
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17:03
Bertl
evening folks!
17:03
apurvanandan[m]
Meeting Time?
17:03
Bertl
yup, in 5 minutes :)
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niemand
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aSobhy
evening
17:09
Bertl
okay, sorry for being late ...
17:09
se6astian|away
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17:09
apurvanandan[m]
no problem
17:09
Bertl
so, today I'd like to focus on how to program the FPGAs and how to do some testing on the hardware (remote and local)
17:11
Bertl
in both tasks, there is a need to program a MachXO2 which is not directly accessible
17:11
Bertl
i.e. you cannot just connect a JTAG programmer and program it
17:13
Bertl
the plugin modules (USB 3.x) have to be programmed through the low speed GPIO pins of the plugin interface
17:14
Bertl
a breakout board can help here and allow access to the JTAG interface, but for the final setup, the MachXO2 needs to be programmed via the Beta
17:15
Bertl
and for the routing fabrics, it's even worse, there we do not even have a way to 'connect' to the JTAG port from outside, except for a tiny header which can be connected to wires on dedicated hardware
17:16
Bertl
so, how can we do that? any suggestions, ideas, etc?
17:18
apurvanandan[m]
Aren't the RFs programed by PIC microcontroller?
17:18
Bertl
correct, there we have two PIC16 connected to the MachXO2s
17:18
Bertl
any idea how the programming works there?
17:19
Y_G
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17:19
Bertl
or to rephrase the question, do you have an idea how you could use PIC16s to program a MachXO2 via JTAG?
17:21
apurvanandan[m]
First we program the PIC which in turn makes RFs programmable by python script running on Zynq?
17:21
apurvanandan[m]
Maybe I am wrong here
17:22
Bertl
no, that's actually how it works
17:22
Bertl
the details are a little trickier, but that's what I'm going to explain
17:23
Bertl
so the PIC16 are connected via three wires, one is a reset called #MCLR
17:23
Bertl
the other two are 'programming' pins called PCLK (clock) and PDAT (data)
17:24
Bertl
the two programming pins can be used as general purpose pins when the PIC is up and running
17:25
Bertl
so we could for example program the PIC16 and then use an UART protocol to 'talk' to the PIC16
17:26
Bertl
but back when this was first implemented, I opted for I2C and the pins are properly terminated to make high speed I2C possible
17:26
Bertl
so there are two protocols spoken on those two wires (PDAT, PCLK)
17:27
Bertl
first the ICSP protocol (in curcuit serial programming) used to program the PIC16
17:28
Bertl
and once the PIC16 is running, the second protocol, I2C, is active
17:28
Bertl
the PIC16 is programmed in such way that it acts as I2C slave
17:29
Bertl
showing up at a range of addresses, which all have specific functions
17:29
Bertl
we'll come to that when we need it
17:29
Bertl
so, any idea how we can do JTAG over I2C?
17:32
apurvanandan[m]
Nope ^^'
17:32
apurvanandan[m]
aSobhy: you around?
17:32
aSobhy
yes
17:33
Bertl
any idea how JTAG works?
17:35
aSobhy
we can use the SCL to be TCK
17:36
aSobhy
and SDA to be TDI ?
17:36
Bertl
hehe, no, we don't want to use an I2C bus as JTAG
17:37
Bertl
we have the situation that a full JTAG port (TMS, TDI, TDO, TCK) is connected to the PIC16 at one side
17:37
Bertl
and the I2C bus (SCL, SDA) is connected to the Zynq on the other end
17:38
Bertl
the problem now is to 'control' the JTAG, via the PIC, but do this over I2C :)
17:40
aSobhy
ah okay
17:41
Bertl
so any idea how JTAG works?
17:42
aSobhy
so we need to convert from I2C to JTAG (that's the python script apurvanandan[m] was talking about )
17:44
aSobhy
TMS & TCK are shared
17:44
aSobhy
TDI & TDO Chained
17:45
Bertl
okay, so there is a clock (TCK) and there is data
17:45
Bertl
there are two inputs to a JTAG device (TDI and TMS)
17:45
Bertl
and there is one output called TDO
17:46
Bertl
both TDI and TMS are shifted into a (shift) register at the TCK clock rate
17:47
Bertl
at the same time the data from the TDI shift register is shifted out via TDO
17:48
Bertl
the other shift register (the one TMS is shifted in) is called the tap controller
17:49
Bertl
it controls a state engine which basically tells the device what kind of data it will receive or transmit
17:50
Bertl
the JTAG state engine is quite complex but kind of symmetrical so once you get the idea, it is not too hard to understand
17:50
Bertl
you should definitely take a closer look in the next few days :)
17:51
Bertl
the simplified 'version' is we need to send bit sequences of (kind of) arbitrary length via TMS and TDI
17:52
Bertl
and while TMS and TDI are basically operating in parallel, thanks to the state engine, we can either send TMS data or TDI data (and keep the other line constant)
17:52
Bertl
(a little simplified here, but that's not a problem)
17:52
Bertl
as I2C is basically 8 bit data
17:53
Bertl
it makes sense to break down the strings of arbitrary length into 8bit chunks plus whatever remains at the end
17:54
Bertl
this is also implemented in the I2C slave in the PIC, so certain addresses result in either a full byte or less than eight bit being sent (or retrieved) via JTAG
17:55
Bertl
as mentioned several times, there are scripts which do certain JTAG operations, including programming the MachXO2s via those I2C registers
17:56
Bertl
we will test this via a remote session in the next few days once the remote Betas are hooked up
17:57
Bertl
now there are two 'ways' to load the bitstream into the MachXO2 ... anybody knows what they are and how they differ?
18:03
apurvanandan[m]
Background mode and off mode
18:03
apurvanandan[m]
?
18:04
Bertl
well, yeah, that's not exactly what I meant but it is related
18:04
Bertl
basically there is a flash memory in the MachXO2 and an SRAM
18:05
Bertl
and as most FPGA, the active configuration is always based on the SRAM
18:05
Bertl
so when the device is reset, the content from the flash is copied (or unpacked) into the SRAM
18:06
Bertl
so programming can be done in two ways, by programming the flash and by directly loading the bitstream into SRAM
18:08
Bertl
now while the PICs can be reprogrammed over and over again
18:09
Bertl
the MachXO2 have a somewhat limited amount of program cycles for the flash
18:09
Bertl
so for development, if possible, you want to use the direct upload to SRAM instead of flashing the bitstream
18:10
Bertl
now while the scripts and PIC code are sufficient for aSobhy's task (programming the routing fabrics)
18:11
Bertl
things become a little more complicated for the MachXO2s on the plugin boards
18:11
Bertl
any idea why?
18:12
apurvanandan[m]
I need to use a programmer?
18:12
Bertl
well, you can do that when you have the plugin in the breakout board (that's what it is for)
18:13
Bertl
but once the plugin gets installed in a Beta (and we will have two of them for testing) it's a little trickier
18:13
Bertl
what would be the process/path there?
18:13
aSobhy
because I have 2 MachX02
18:13
apurvanandan[m]
We will use a special pass through code on RFs
18:14
Bertl
yep, precisely
18:14
apurvanandan[m]
<Bertl "what would be the process/path t"> Till aSobhy doesn't completes the bidirectional protocol
18:14
Bertl
once aSobhy finishes some kind of JTAG interface via the RFs, we can hopefully use that
18:15
Bertl
apurvanandan[m]: do you also remember how the pass through works?
18:16
apurvanandan[m]
What's in the pass through code or how to use it?
18:16
Bertl
why not both :)
18:18
apurvanandan[m]
It is uploaded on RFE the same way as discussed, then after that all signals we send to RFE are forwarded to plugin module's single io pins, some switching on PIC is required maybe
18:19
Bertl
that is basically correct except for a small detail
18:19
apurvanandan[m]
I have gone through the codes somewhere on github repo but I don't remember at the moment
18:20
Bertl
can you check the schematics which pins of RFE are connected to the plugin slots?
18:20
aSobhy
sorry i'm confused, are we talking in two different topics ?
18:21
apurvanandan[m]
Haven't opened schematics of main board yet. It will take time.
18:21
Bertl
aSobhy: no, what's the confusion?
18:23
aSobhy
what is programmer apurvanandan[m] talking about ?!
18:24
aSobhy
I don't understand from then
18:24
Bertl
about programming the MachXO2 on the USB 3.0 plugin module
18:25
Bertl
https://apertus.org/sites/default/files/images/AXIOM-Beta-PCB-Stack-Trans-04.png
18:26
Bertl
the plugin modules each also contain a MachXO2 (the USB3 ones) which work as gearwork for the FTDI used to connect via USB
18:26
Bertl
they are plugged into the plugin slots of the Beta (on the Mainboard) which connects them to the Zynq and the RF (MachXO2 on the Mainboard)
18:27
aSobhy
ah okay
18:27
Bertl
so basically it is a two-hop from the Zynq to the MachXO2 programming interface on the plugin modules
18:28
Bertl
(and a three hop via the PIC16)
18:29
aSobhy
so the JTAG I'll write will make it 2 hops only
18:29
Bertl
yep, the Zynq then can send (and receive) JTAG data via the MachXO2 interface on the main board
18:30
aSobhy
okay sorry of that misunderstand :)
18:31
Bertl
no problem, it's always good to get an idea what the other students are doing :)
18:34
Bertl
so, aSobhy, maybe you got an idea which pins of RFE are connected to the plugin slots?
18:34
aSobhy
so I'll change the JTAG to be implemented first
18:34
Bertl
(while apurvanandan[m] is searching)
18:35
aSobhy
yes
18:36
Bertl
well, you may prioritize JTAG if you like
18:37
Bertl
but it is definitely more complex than I2C to get started with
18:39
aSobhy
yeah I designed it from easy to hard but I'll do all at the end so no problem!
18:41
Bertl
okay, I guess apurvanandan[m] might appreciate it :)
18:43
Bertl
so back to the RFE pins connected to the plugin slots
18:44
apurvanandan[m]
They are connected to Jtag programming pins directly
18:46
Bertl
sure about that?
18:46
apurvanandan[m]
Of usb plugin module, on RFE I am searching what are those pins of MachXO2
18:53
apurvanandan[m]
I think they are general purpose pins of RFE
18:53
apurvanandan[m]
Yeah, they are GPIOs
18:53
Bertl
and how are the connections labeled?
18:54
apurvanandan[m]
PCIE_N_IO* on RFE
18:57
apurvanandan[m]
Jtag type pins on usb module
18:58
Bertl
okay, except for a small detail, the plugin slots are on the 'West' side not the 'East', so it is RFW not RFE :)
18:59
aSobhy
yes I'll just say that
18:59
apurvanandan[m]
So JTAG protocol is similar to SPI, hence RFE simply forwards it
19:00
apurvanandan[m]
What needs to be sent is changed little
19:00
apurvanandan[m]
To the spi
19:00
Bertl
RFW not RFE :)
19:01
Bertl
and the pass through is actually slighly different in the plugin programming case
19:01
apurvanandan[m]
> RFW not RFE :)
19:01
apurvanandan[m]
Yes , that's confusing
19:01
Bertl
there are a number of PIC16 GPIOs connected to the RFs
19:01
Bertl
(besides the JTAG pins)
19:02
Bertl
and those can be used to send JTAG data _through_ the RFW directly to the plugin slots
19:04
Bertl
okay, so that's been a lot for today, but we have to increase the pace now that we entered the coding phase
19:05
Bertl
if all goes well, the remote Beta should be available tomorrow, so let's plan for Thursday or Friday to have a remote session with programming PICs and MachXO2s
19:06
Bertl
please read up on JTAG and I2C for this purpose and check the schematics again
19:07
apurvanandan[m]
Bertl, won't you see our this week's finds? :)
19:07
Bertl
of course, please share
19:09
aSobhy
in case it will be along meeting I'd prefer Thursday ?!
19:10
Bertl
okay, apurvanandan[m], any preferences?
19:11
apurvanandan[m]
Firstly I found this book that briefs you with all concepts of high speed serial links
19:11
apurvanandan[m]
http://xilinx.eetrend.com/files-eetrend-xilinx/forum/201407/7408-13218-xilinx_serial_io_101_gao_su_chuan_xing_ru_men_.pdf
19:11
apurvanandan[m]
This presentation that explains some topics like training pattern , word alignment etc: https://www.so-logic.net/documents/trainings/01_so_hssio_basics.pdf
19:12
apurvanandan[m]
This paper compares two methods of word recombination ie using delay component and using fifo: http://sci-hub.tw/https://doi.org/10.1109/TCSII.2015.2468992
19:16
Bertl
okay, nice
19:17
apurvan
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19:18
apurvan
Sorry Riot.im is not working properly
19:19
apurvan
I would prefer Friday actually :)
19:20
Bertl
okay, so let's see when the Beta is up and running, and we decide then, be prepared for Thursday or Friday evening
19:20
apurvan
Okay fine
19:21
apurvan
But till then please guide us so that we can atleast start coding
19:21
Bertl
of course, you can already start with a bunch of things you learned
19:21
apurvan
I wrote in my proposal to start coding from May 20, and haven't yet
19:21
Bertl
like for example the PRNG and BER calculations
19:22
Bertl
(they are independent from any protocol and/or physical setup)
19:22
apurvan
PRNG is already implemented by you though
19:23
Bertl
well, you need to integrate it properly
19:23
Bertl
best combine it with a testbench
19:24
Bertl
check with 'local' sender and receiver pairs (in the same FPGA)
19:24
apurvan
Also do we need to follow our timeline exactly, like do every thing in same order?
19:24
Bertl
then introduce some bit error generator
19:24
apurvan
I mentioned to start with ft601q controller
19:25
Bertl
no, we have some flexibility there but we need to match the GSoC deadlines
19:25
apurvan
And also mentioned to show that for the phase 1 evaluation ^^'
19:25
Bertl
(but we have some wiggle room there as well)
19:26
Bertl
I presume you already know the FT60x inside out
19:26
apurvan
Actually no I don't
19:26
Bertl
(at least theoretically)
19:26
aSobhy
actually its hard for me to start coding till Sunday(2-6) 4 days remaining :(
19:27
Bertl
how's that?
19:27
Bertl
(I mean, why is it hard?)
19:28
aSobhy
still 2 exams (Thursday and Sunday)
19:29
Bertl
well, that's something you knew when you applied
19:30
Bertl
anyway, GSoC is not simple, so try your best there as well as with any other exams or tasks
19:31
apurvan
This week I read properly about ft601q.
19:31
Bertl
but as you both will need the test framework, it might make things a lot simpler to work together
19:32
Bertl
i.e. make sure that the code is useable by both parties, this way you can half your efforts
19:32
Bertl
*halve
19:32
apurvan
Yes i agree fully
19:33
apurvan
Ok will chat with aSobhy and start coding from tomorrow.
19:33
Bertl
apurvan: if you like, you can prepare a small presentation about the FT60x for next week?
19:34
apurvan
What type and for what( for some official reason?)
19:34
aSobhy
OK, what tools we will use for the remote meeting ? (and we will use linux )
19:35
Bertl
kind of overview/summary of the datasheet, how the thing works and what it does ... how the interface looks like
19:35
apurvan
changed nick to: apurvanandan
19:35
Bertl
for the remote meeting we will use ssh/screen
19:36
Bertl
(and IRC of course, but a separate channel)
19:36
Bertl
so if you haven't done so already, send me your public ssh keys
19:36
Bertl
and check (with me in private) that they actually work
19:37
apurvanandan
And how will I present that?
19:38
aSobhy
I have tried before and it works I'm asking because i didn't free some space on Ubuntu (needs to formate) so no vivado or lattice on linux
19:38
Bertl
however you like ... IRC chat, conversional style or if you prefer with (PDF) slides or whatever you like
19:38
Bertl
aSobhy: we won't need the tools for this
19:39
aSobhy
OK, thanks :)
19:39
Bertl
but it won't hurt to start cleaning up :)
19:40
aSobhy
hhhhhhhh yeah I know
19:41
Bertl
okay, any unanswered questions left?
19:42
apurvanandan[m]
`I have sent my ssh key
19:42
aSobhy
It's all about the disk is full and I'll give Ubuntu some space so I'll re-partition the disk
19:46
apurvanandan[m]
<Bertl "okay, any unanswered questions l"> Nope, Thanks for your time!
19:49
Bertl
you're welcome!
19:49
aSobhy
Bertl: how can we save the meeting chat
19:50
Bertl
as we are on the public channel, it is automatically logged
19:50
Bertl
so you can look it up on irc.apertus.org
19:50
aSobhy
by the logs on the server I think se6astian said we are saving it and post it in the meeting group
19:51
aSobhy
google groups
19:51
Bertl
yes, that might happen again, i.e. some reference to the irc logs or a short summary
19:52
aSobhy
I think you don't have time to do so I can help :)
19:53
Bertl
no problem, just check with se6astian
19:54
aSobhy
OK,
19:54
aSobhy
Thanks Bertl for your time :)
19:55
Bertl
my pleasure!
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23:28
Bertl
off to bed now ... have a good one everyone!
23:29
Bertl
changed nick to: Bertl_zZ