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07:59 | Bertl | morning folks!
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07:59 | apurvanandan[m] | Good morning!
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08:41 | se6astian | good day
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10:26 | Dev_ | Hello Bandit1983 , sorry I wasn't able to attend the yesterday's meeting , could u able to check my email . Any feedback ??
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10:28 | Bertl | off for now ... bbl
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16:47 | BAndiT1983 | hi Dev_, i've replied to your email yesterday already, please check your spam folder, as Supragya retrieved it from his
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18:03 | Bertl | evening folks!
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18:03 | apurvanandan[m] | Meeting Time?
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18:03 | Bertl | yup, in 5 minutes :)
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18:04 | aSobhy | evening
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18:09 | Bertl | okay, sorry for being late ...
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18:09 | apurvanandan[m] | no problem
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18:09 | Bertl | so, today I'd like to focus on how to program the FPGAs and how to do some testing on the hardware (remote and local)
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18:11 | Bertl | in both tasks, there is a need to program a MachXO2 which is not directly accessible
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18:11 | Bertl | i.e. you cannot just connect a JTAG programmer and program it
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18:13 | Bertl | the plugin modules (USB 3.x) have to be programmed through the low speed GPIO pins of the plugin interface
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18:14 | Bertl | a breakout board can help here and allow access to the JTAG interface, but for the final setup, the MachXO2 needs to be programmed via the Beta
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18:15 | Bertl | and for the routing fabrics, it's even worse, there we do not even have a way to 'connect' to the JTAG port from outside, except for a tiny header which can be connected to wires on dedicated hardware
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18:16 | Bertl | so, how can we do that? any suggestions, ideas, etc?
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18:18 | apurvanandan[m] | Aren't the RFs programed by PIC microcontroller?
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18:18 | Bertl | correct, there we have two PIC16 connected to the MachXO2s
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18:18 | Bertl | any idea how the programming works there?
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18:19 | Bertl | or to rephrase the question, do you have an idea how you could use PIC16s to program a MachXO2 via JTAG?
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18:21 | apurvanandan[m] | First we program the PIC which in turn makes RFs programmable by python script running on Zynq?
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18:21 | apurvanandan[m] | Maybe I am wrong here
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18:22 | Bertl | no, that's actually how it works
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18:22 | Bertl | the details are a little trickier, but that's what I'm going to explain
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18:23 | Bertl | so the PIC16 are connected via three wires, one is a reset called #MCLR
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18:23 | Bertl | the other two are 'programming' pins called PCLK (clock) and PDAT (data)
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18:24 | Bertl | the two programming pins can be used as general purpose pins when the PIC is up and running
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18:25 | Bertl | so we could for example program the PIC16 and then use an UART protocol to 'talk' to the PIC16
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18:26 | Bertl | but back when this was first implemented, I opted for I2C and the pins are properly terminated to make high speed I2C possible
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18:26 | Bertl | so there are two protocols spoken on those two wires (PDAT, PCLK)
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18:27 | Bertl | first the ICSP protocol (in curcuit serial programming) used to program the PIC16
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18:28 | Bertl | and once the PIC16 is running, the second protocol, I2C, is active
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18:28 | Bertl | the PIC16 is programmed in such way that it acts as I2C slave
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18:29 | Bertl | showing up at a range of addresses, which all have specific functions
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18:29 | Bertl | we'll come to that when we need it
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18:29 | Bertl | so, any idea how we can do JTAG over I2C?
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18:32 | apurvanandan[m] | Nope ^^'
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18:32 | apurvanandan[m] | aSobhy: you around?
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18:32 | aSobhy | yes
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18:33 | Bertl | any idea how JTAG works?
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18:35 | aSobhy | we can use the SCL to be TCK
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18:36 | aSobhy | and SDA to be TDI ?
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18:36 | Bertl | hehe, no, we don't want to use an I2C bus as JTAG
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18:37 | Bertl | we have the situation that a full JTAG port (TMS, TDI, TDO, TCK) is connected to the PIC16 at one side
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18:37 | Bertl | and the I2C bus (SCL, SDA) is connected to the Zynq on the other end
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18:38 | Bertl | the problem now is to 'control' the JTAG, via the PIC, but do this over I2C :)
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18:40 | aSobhy | ah okay
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18:41 | Bertl | so any idea how JTAG works?
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18:42 | aSobhy | so we need to convert from I2C to JTAG (that's the python script apurvanandan[m] was talking about )
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18:44 | aSobhy | TMS & TCK are shared
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18:44 | aSobhy | TDI & TDO Chained
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18:45 | Bertl | okay, so there is a clock (TCK) and there is data
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18:45 | Bertl | there are two inputs to a JTAG device (TDI and TMS)
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18:45 | Bertl | and there is one output called TDO
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18:46 | Bertl | both TDI and TMS are shifted into a (shift) register at the TCK clock rate
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18:47 | Bertl | at the same time the data from the TDI shift register is shifted out via TDO
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18:48 | Bertl | the other shift register (the one TMS is shifted in) is called the tap controller
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18:49 | Bertl | it controls a state engine which basically tells the device what kind of data it will receive or transmit
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18:50 | Bertl | the JTAG state engine is quite complex but kind of symmetrical so once you get the idea, it is not too hard to understand
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18:50 | Bertl | you should definitely take a closer look in the next few days :)
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18:51 | Bertl | the simplified 'version' is we need to send bit sequences of (kind of) arbitrary length via TMS and TDI
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18:52 | Bertl | and while TMS and TDI are basically operating in parallel, thanks to the state engine, we can either send TMS data or TDI data (and keep the other line constant)
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18:52 | Bertl | (a little simplified here, but that's not a problem)
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18:52 | Bertl | as I2C is basically 8 bit data
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18:53 | Bertl | it makes sense to break down the strings of arbitrary length into 8bit chunks plus whatever remains at the end
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18:54 | Bertl | this is also implemented in the I2C slave in the PIC, so certain addresses result in either a full byte or less than eight bit being sent (or retrieved) via JTAG
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18:55 | Bertl | as mentioned several times, there are scripts which do certain JTAG operations, including programming the MachXO2s via those I2C registers
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18:56 | Bertl | we will test this via a remote session in the next few days once the remote Betas are hooked up
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18:57 | Bertl | now there are two 'ways' to load the bitstream into the MachXO2 ... anybody knows what they are and how they differ?
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19:03 | apurvanandan[m] | Background mode and off mode
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19:03 | apurvanandan[m] | ?
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19:04 | Bertl | well, yeah, that's not exactly what I meant but it is related
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19:04 | Bertl | basically there is a flash memory in the MachXO2 and an SRAM
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19:05 | Bertl | and as most FPGA, the active configuration is always based on the SRAM
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19:05 | Bertl | so when the device is reset, the content from the flash is copied (or unpacked) into the SRAM
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19:06 | Bertl | so programming can be done in two ways, by programming the flash and by directly loading the bitstream into SRAM
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19:08 | Bertl | now while the PICs can be reprogrammed over and over again
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19:09 | Bertl | the MachXO2 have a somewhat limited amount of program cycles for the flash
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19:09 | Bertl | so for development, if possible, you want to use the direct upload to SRAM instead of flashing the bitstream
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19:10 | Bertl | now while the scripts and PIC code are sufficient for aSobhy's task (programming the routing fabrics)
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19:11 | Bertl | things become a little more complicated for the MachXO2s on the plugin boards
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19:11 | Bertl | any idea why?
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19:12 | apurvanandan[m] | I need to use a programmer?
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19:12 | Bertl | well, you can do that when you have the plugin in the breakout board (that's what it is for)
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19:13 | Bertl | but once the plugin gets installed in a Beta (and we will have two of them for testing) it's a little trickier
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19:13 | Bertl | what would be the process/path there?
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19:13 | aSobhy | because I have 2 MachX02
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19:13 | apurvanandan[m] | We will use a special pass through code on RFs
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19:14 | Bertl | yep, precisely
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19:14 | apurvanandan[m] | <Bertl "what would be the process/path t"> Till aSobhy doesn't completes the bidirectional protocol
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19:14 | Bertl | once aSobhy finishes some kind of JTAG interface via the RFs, we can hopefully use that
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19:15 | Bertl | apurvanandan[m]: do you also remember how the pass through works?
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19:16 | apurvanandan[m] | What's in the pass through code or how to use it?
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19:16 | Bertl | why not both :)
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19:18 | apurvanandan[m] | It is uploaded on RFE the same way as discussed, then after that all signals we send to RFE are forwarded to plugin module's single io pins, some switching on PIC is required maybe
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19:19 | Bertl | that is basically correct except for a small detail
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19:19 | apurvanandan[m] | I have gone through the codes somewhere on github repo but I don't remember at the moment
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19:20 | Bertl | can you check the schematics which pins of RFE are connected to the plugin slots?
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19:20 | aSobhy | sorry i'm confused, are we talking in two different topics ?
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19:21 | apurvanandan[m] | Haven't opened schematics of main board yet. It will take time.
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19:21 | Bertl | aSobhy: no, what's the confusion?
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19:23 | aSobhy | what is programmer apurvanandan[m] talking about ?!
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19:24 | aSobhy | I don't understand from then
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19:24 | Bertl | about programming the MachXO2 on the USB 3.0 plugin module
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19:25 | Bertl | https://apertus.org/sites/default/files/images/AXIOM-Beta-PCB-Stack-Trans-04.png
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19:26 | Bertl | the plugin modules each also contain a MachXO2 (the USB3 ones) which work as gearwork for the FTDI used to connect via USB
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19:26 | Bertl | they are plugged into the plugin slots of the Beta (on the Mainboard) which connects them to the Zynq and the RF (MachXO2 on the Mainboard)
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19:27 | aSobhy | ah okay
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19:27 | Bertl | so basically it is a two-hop from the Zynq to the MachXO2 programming interface on the plugin modules
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19:28 | Bertl | (and a three hop via the PIC16)
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19:29 | aSobhy | so the JTAG I'll write will make it 2 hops only
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19:29 | Bertl | yep, the Zynq then can send (and receive) JTAG data via the MachXO2 interface on the main board
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19:30 | aSobhy | okay sorry of that misunderstand :)
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19:31 | Bertl | no problem, it's always good to get an idea what the other students are doing :)
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19:34 | Bertl | so, aSobhy, maybe you got an idea which pins of RFE are connected to the plugin slots?
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19:34 | aSobhy | so I'll change the JTAG to be implemented first
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19:34 | Bertl | (while apurvanandan[m] is searching)
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19:35 | aSobhy | yes
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19:36 | Bertl | well, you may prioritize JTAG if you like
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19:37 | Bertl | but it is definitely more complex than I2C to get started with
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19:39 | aSobhy | yeah I designed it from easy to hard but I'll do all at the end so no problem!
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19:41 | Bertl | okay, I guess apurvanandan[m] might appreciate it :)
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19:43 | Bertl | so back to the RFE pins connected to the plugin slots
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19:44 | apurvanandan[m] | They are connected to Jtag programming pins directly
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19:46 | Bertl | sure about that?
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19:46 | apurvanandan[m] | Of usb plugin module, on RFE I am searching what are those pins of MachXO2
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19:53 | apurvanandan[m] | I think they are general purpose pins of RFE
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19:53 | apurvanandan[m] | Yeah, they are GPIOs
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19:53 | Bertl | and how are the connections labeled?
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19:54 | apurvanandan[m] | PCIE_N_IO* on RFE
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19:57 | apurvanandan[m] | Jtag type pins on usb module
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19:58 | Bertl | okay, except for a small detail, the plugin slots are on the 'West' side not the 'East', so it is RFW not RFE :)
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19:59 | aSobhy | yes I'll just say that
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19:59 | apurvanandan[m] | So JTAG protocol is similar to SPI, hence RFE simply forwards it
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20:00 | apurvanandan[m] | What needs to be sent is changed little
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20:00 | apurvanandan[m] | To the spi
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20:00 | Bertl | RFW not RFE :)
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20:01 | Bertl | and the pass through is actually slighly different in the plugin programming case
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20:01 | apurvanandan[m] | > RFW not RFE :)
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20:01 | apurvanandan[m] | Yes , that's confusing
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20:01 | Bertl | there are a number of PIC16 GPIOs connected to the RFs
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20:01 | Bertl | (besides the JTAG pins)
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20:02 | Bertl | and those can be used to send JTAG data _through_ the RFW directly to the plugin slots
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20:04 | Bertl | okay, so that's been a lot for today, but we have to increase the pace now that we entered the coding phase
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20:05 | Bertl | if all goes well, the remote Beta should be available tomorrow, so let's plan for Thursday or Friday to have a remote session with programming PICs and MachXO2s
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20:06 | Bertl | please read up on JTAG and I2C for this purpose and check the schematics again
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20:07 | apurvanandan[m] | Bertl, won't you see our this week's finds? :)
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20:07 | Bertl | of course, please share
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20:09 | aSobhy | in case it will be along meeting I'd prefer Thursday ?!
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20:10 | Bertl | okay, apurvanandan[m], any preferences?
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20:11 | apurvanandan[m] | Firstly I found this book that briefs you with all concepts of high speed serial links
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20:11 | apurvanandan[m] | http://xilinx.eetrend.com/files-eetrend-xilinx/forum/201407/7408-13218-xilinx_serial_io_101_gao_su_chuan_xing_ru_men_.pdf
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20:11 | apurvanandan[m] | This presentation that explains some topics like training pattern , word alignment etc: https://www.so-logic.net/documents/trainings/01_so_hssio_basics.pdf
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20:12 | apurvanandan[m] | This paper compares two methods of word recombination ie using delay component and using fifo: http://sci-hub.tw/https://doi.org/10.1109/TCSII.2015.2468992
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20:16 | Bertl | okay, nice
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20:18 | apurvan | Sorry Riot.im is not working properly
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20:19 | apurvan | I would prefer Friday actually :)
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20:20 | Bertl | okay, so let's see when the Beta is up and running, and we decide then, be prepared for Thursday or Friday evening
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20:20 | apurvan | Okay fine
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20:21 | apurvan | But till then please guide us so that we can atleast start coding
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20:21 | Bertl | of course, you can already start with a bunch of things you learned
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20:21 | apurvan | I wrote in my proposal to start coding from May 20, and haven't yet
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20:21 | Bertl | like for example the PRNG and BER calculations
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20:22 | Bertl | (they are independent from any protocol and/or physical setup)
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20:22 | apurvan | PRNG is already implemented by you though
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20:23 | Bertl | well, you need to integrate it properly
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20:23 | Bertl | best combine it with a testbench
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20:24 | Bertl | check with 'local' sender and receiver pairs (in the same FPGA)
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20:24 | apurvan | Also do we need to follow our timeline exactly, like do every thing in same order?
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20:24 | Bertl | then introduce some bit error generator
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20:24 | apurvan | I mentioned to start with ft601q controller
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20:25 | Bertl | no, we have some flexibility there but we need to match the GSoC deadlines
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20:25 | apurvan | And also mentioned to show that for the phase 1 evaluation ^^'
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20:25 | Bertl | (but we have some wiggle room there as well)
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20:26 | Bertl | I presume you already know the FT60x inside out
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20:26 | apurvan | Actually no I don't
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20:26 | Bertl | (at least theoretically)
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20:26 | aSobhy | actually its hard for me to start coding till Sunday(2-6) 4 days remaining :(
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20:27 | Bertl | how's that?
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20:27 | Bertl | (I mean, why is it hard?)
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20:28 | aSobhy | still 2 exams (Thursday and Sunday)
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20:29 | Bertl | well, that's something you knew when you applied
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20:30 | Bertl | anyway, GSoC is not simple, so try your best there as well as with any other exams or tasks
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20:31 | apurvan | This week I read properly about ft601q.
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20:31 | Bertl | but as you both will need the test framework, it might make things a lot simpler to work together
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20:32 | Bertl | i.e. make sure that the code is useable by both parties, this way you can half your efforts
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20:32 | Bertl | *halve
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20:32 | apurvan | Yes i agree fully
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20:33 | apurvan | Ok will chat with aSobhy and start coding from tomorrow.
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20:33 | Bertl | apurvan: if you like, you can prepare a small presentation about the FT60x for next week?
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20:34 | apurvan | What type and for what( for some official reason?)
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20:34 | aSobhy | OK, what tools we will use for the remote meeting ? (and we will use linux )
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20:35 | Bertl | kind of overview/summary of the datasheet, how the thing works and what it does ... how the interface looks like
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20:35 | apurvan | changed nick to: apurvanandan
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20:35 | Bertl | for the remote meeting we will use ssh/screen
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20:36 | Bertl | (and IRC of course, but a separate channel)
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20:36 | Bertl | so if you haven't done so already, send me your public ssh keys
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20:36 | Bertl | and check (with me in private) that they actually work
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20:37 | apurvanandan | And how will I present that?
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20:38 | aSobhy | I have tried before and it works I'm asking because i didn't free some space on Ubuntu (needs to formate) so no vivado or lattice on linux
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20:38 | Bertl | however you like ... IRC chat, conversional style or if you prefer with (PDF) slides or whatever you like
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20:38 | Bertl | aSobhy: we won't need the tools for this
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20:39 | aSobhy | OK, thanks :)
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20:39 | Bertl | but it won't hurt to start cleaning up :)
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20:40 | aSobhy | hhhhhhhh yeah I know
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20:41 | Bertl | okay, any unanswered questions left?
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20:42 | apurvanandan[m] | `I have sent my ssh key
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20:42 | aSobhy | It's all about the disk is full and I'll give Ubuntu some space so I'll re-partition the disk
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20:46 | apurvanandan[m] | <Bertl "okay, any unanswered questions l"> Nope, Thanks for your time!
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20:49 | Bertl | you're welcome!
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20:49 | aSobhy | Bertl: how can we save the meeting chat
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20:50 | Bertl | as we are on the public channel, it is automatically logged
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20:50 | Bertl | so you can look it up on irc.apertus.org
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20:50 | aSobhy | by the logs on the server I think se6astian said we are saving it and post it in the meeting group
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20:51 | aSobhy | google groups
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20:51 | Bertl | yes, that might happen again, i.e. some reference to the irc logs or a short summary
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20:52 | aSobhy | I think you don't have time to do so I can help :)
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20:53 | Bertl | no problem, just check with se6astian
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20:54 | aSobhy | OK,
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20:54 | aSobhy | Thanks Bertl for your time :)
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20:55 | Bertl | my pleasure!
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00:28 | Bertl | off to bed now ... have a good one everyone!
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00:29 | Bertl | changed nick to: Bertl_zZ
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