#apertus IRC Channel Logs

hi Niels_so

Hi everybody ! Hi Dave, you can contact me at guillaume(at)chooksprod.com if you want, i'm a french near Annecy. If we organize a maker faire in Lyon it will be good to be a group to know the camera. if it's sound interesting for you !

Hello

hi joy_!

Thank you very much...As soon I complete one of the task what should I do then

morning folks!

Hello I think you are the proposed mentor of the FPGA projects

make sure to deliver clean code (T871) which uses a coding style similar to the exitsting VHDL code

that together with the application for GSoC will be the basis for our selection

Please help me out what should I learn/ do after completing the task

See links to reading here - https://wiki.apertus.org/index.php/GSoC_Overview

please do so and have fun!

Bertl: is completing the GSoC mandatory? Or can I contribute on FPGA tasks without?

ok, thank you :-)

Bertl: are the FPGA chosen for a given task following this rule: Zynq for image and high-speed signals processing, Lattice for signal conversion/low-area IPs?

Hello

Was the code sent good enough?

I was planning to complete one more task...

Thank you

so make sure to use proper coding style, think twice about all your decisions, if necessary, start from scratch based on the ideas you gathered on the previous attempt, etc

Point noted....I will check the I2C code again and remake it if needed

hint here: writing a coding style guide might be something worth doing (benefits the project and helps you understand it at the same time)

indeed, we selected the FPGAs based on how nicely they fit the purpose

Zynq was kind of given as back then the MicroZed was the only affordable (well documented) development board with enough I/Os

So Should I also implement a frequency divider as I know that I2C works on max 400 KHz...Or the SCL will be of max 400KHz frequency

I'm looking at your code right now, first thing I see there is that you want to work on your indentation

you too!

thanks!

Okay so as the master has the control on SCL and SDA lines the frequency of the system clock in the code need not be changed..

Thank you

I am sorry Bertl:

it is a good idea to check here on a regular basis

Made some changes in the code indentation and added comments

https://raw.githubusercontent.com/Manas173/PWM-generator-and-I2C_slave/master/i2c_slave_pwm_control.vhd ?

here some input on that (indentation and other things):

Ok I am on it...replying you as soon as it is completed

Okay , point noted

you can, and probably should use a 4 space indentation instead of 8 spaces to keep the code within 80 characters

Thats to point them out...I am working on it

Okay

Kjetil: To send an ack bit to the master

The 7 bit address for each i2c slave register is a unique one so there will at max one slave address that will match

i.e. you never actively put power (e.g. a '1') on the bus

A error from my side apologies...I am correcting that

Thank you I will correct that immedeately

Commit the changes, made the changes in the code indentation and sda line floating as mentioned

check code style for line 36, 62, 67, 89 and indentation for 93, 105-119, 126 and more

That was my silly mistake Adding the copyright notice and license

Kjetil: Sorry but do you mean why i used the falling edge of SDA and simultaneously checked for the scl to be high or not...Well its the start condition

To do tasks such as changing the state etc.

which is something you cannot assume with I2C

I guess you might get a FF on the SCL line and the data outsignal from that will be used as a clock in the next FFs

With at edge driven implementation the meta stable region will be an issue when the 'system' clock is fast compared to the i2c clock

that would certainly work for the i2c slave but pose some serious challenges for the PWM side

but I would rather suggest to sample SCL with your system clock and act based on changes there

not sure what you're trying to say, but you cannot make any assumptions on SCL except that it will be below 1MHz (400kHz)

I will look into this problem and will reply you soon enough.

no problem!

Did the changes , now the I2C runs only the scl clock and not the system clock and data transfer takes place to pwm controller which is running on system clock. Made a branch and a copyright GNU GPL license Link : https://github.com/Manas173/PWM-generator-and-I2C_slave/tree/add-license-1

Kjetil and Bertl : I will about it very soon Thanks for guidance

you're welcome!

Licensed both the master and a new branch : https://github.com/Manas173/PWM-generator-and-I2C_slave/tree/branch-1 Sorry the above was deleted

off for now ... bbl

good night