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| 08:46 | Niels_so | Good morning
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| 08:48 | se6astian | hi Niels_so
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| 08:50 | Rex0r | Hey Dave.
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| 10:46 | Guillaume_Chooks | Hi everybody ! Hi Dave, you can contact me at guillaume(at)chooksprod.com if you want, i'm a french near Annecy. If we organize a maker faire in Lyon it will be good to be a group to know the camera. if it's sound interesting for you !
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| 10:47 | Guillaume_Chooks | I'm working for now but d'ont hesitate to contact me !
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| 11:42 | joy_ | Hello
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| 11:45 | joy_ | Is anyone here? I am interested on USB interface using FPGA project where should I start?
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| 11:46 | se6astian | hi joy_!
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| 11:47 | se6astian | if you want to apply for GSoC for this task the best starting point is completing the FPGA/VHDL challenge: https://lab.apertus.org/T871
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| 11:49 | joy_ | Thank you very much...As soon I complete one of the task what should I do then
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| 11:50 | Bertl_zZ | changed nick to: Bertl
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| 11:51 | Bertl | morning folks!
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| 11:51 | Niels_so | Hi Bertl
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| 11:52 | joy_ | Hello I think you are the proposed mentor of the FPGA projects
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| 11:52 | Bertl | you are correct about that :)
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| 11:53 | Bertl | make sure to deliver clean code (T871) which uses a coding style similar to the exitsting VHDL code
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| 11:53 | Bertl | note: you can also do more than one of the qualification tasks (if you feel like it)
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| 11:54 | Bertl | that together with the application for GSoC will be the basis for our selection
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| 11:55 | Bertl | do not hesitate to ask if you have any questions
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| 11:56 | joy_ | Please help me out what should I learn/ do after completing the task
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| 11:59 | Bertl | when you are finished with the qualification task(s), it is probably a good idea to make yourself comfortable with the hardware (online documentation, asking here, etc) and the task you are interested in (USB interface)
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| 12:00 | Rex0r | See links to reading here - https://wiki.apertus.org/index.php/GSoC_Overview
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| 12:02 | joy_ | Thank you I will contact if I face any problem
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| 12:02 | Bertl | please do so and have fun!
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| 12:08 | Niels_so | Bertl: is completing the GSoC mandatory? Or can I contribute on FPGA tasks without?
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| 12:09 | Bertl | nothing is mandatory, you can always contribute/work on anything you like
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| 12:09 | Niels_so | ok, thank you :-)
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| 12:12 | Bertl | no problem
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| 12:13 | Niels_so | Bertl: are the FPGA chosen for a given task following this rule: Zynq for image and high-speed signals processing, Lattice for signal conversion/low-area IPs?
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| 12:13 | Niels_so | (just wondering, that's something I see on some projects as well)
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| 12:15 | manas | joined the channel |
| 12:15 | manas | Hello
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| 12:16 | Bertl | hello manas!
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| 12:16 | manas | Was the code sent good enough?
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| 12:16 | Bertl | I haven't checked it yet, but I will do so shortly
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| 12:16 | manas | I was planning to complete one more task...
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| 12:17 | Bertl | you are definitely ahead of GSoC :)
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| 12:17 | manas | Thank you
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| 12:18 | Bertl | note: having more than one qualification task is nice, but handing in a perfect one is way better
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| 12:19 | Bertl | so make sure to use proper coding style, think twice about all your decisions, if necessary, start from scratch based on the ideas you gathered on the previous attempt, etc
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| 12:19 | Bertl | in short, it is more about quality than quantity
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| 12:20 | manas | Point noted....I will check the I2C code again and remake it if needed
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| 12:21 | Bertl | I know that we do not have a coding style guide (yet) but you can always ask me if something is unclear
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| 12:22 | Bertl | hint here: writing a coding style guide might be something worth doing (benefits the project and helps you understand it at the same time)
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| 12:23 | se6astian | (2:13:09 PM) Niels_so: Bertl: are the FPGA chosen for a given task following this rule: Zynq for image and high-speed signals processing, Lattice for signal conversion/low-area IPs? <- yes thats also our approach, correct me if I am wrong, Bertl
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| 12:24 | Bertl | indeed, we selected the FPGAs based on how nicely they fit the purpose
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| 12:25 | manas | Bertyl : Regarding the I2C: apart from sda and SCL I have used a clock (system clock)of frequency 100 MHz...
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| 12:25 | Bertl | Zynq was kind of given as back then the MicroZed was the only affordable (well documented) development board with enough I/Os
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| 12:26 | Bertl | manas: that's fine, some kind of system clock will always be present, just make sure that there are no problems with synchronization/clock domain crossings
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| 12:28 | manas | So Should I also implement a frequency divider as I know that I2C works on max 400 KHz...Or the SCL will be of max 400KHz frequency
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| 12:29 | manas | That is, the frequency given from the master by the SCL line will be of 400Hz right? So should bother of the system clock frequency divider?
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| 12:29 | Bertl | I'm looking at your code right now, first thing I see there is that you want to work on your indentation
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| 12:29 | Niels_so | se6astian, Bertl : ok, thank you. Have a good afternonn!
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| 12:29 | Bertl | you too!
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| 12:29 | Niels_so | afternoon*
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| 12:29 | Niels_so | thanks!
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| 12:30 | Bertl | manas: no, the master can use anything below 1MHz (or 400kHz)
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| 12:35 | manas | Okay so as the master has the control on SCL and SDA lines the frequency of the system clock in the code need not be changed..
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| 12:39 | manas | I will work on the code indentation and provide you a clean code in the future
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| 12:39 | manas | Thank you
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| 12:40 | manas | Beryl: Please let me know if there is any error in the code
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| 12:41 | manas | I am sorry Bertl:
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| 12:41 | Bertl | yes, will go through the code tonight and provide some feedback
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| 12:42 | Bertl | it is a good idea to check here on a regular basis
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| 13:23 | manas | Bertl : Sorry for late reply. I will surely visit here frequently
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| 13:23 | manas | Made some changes in the code indentation and added comments
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| 13:25 | Bertl | URL for the changes?
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| 13:26 | Bertl | https://raw.githubusercontent.com/Manas173/PWM-generator-and-I2C_slave/master/i2c_slave_pwm_control.vhd ?
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| 13:26 | manas | Yes correct
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| 13:27 | Bertl | here some input on that (indentation and other things):
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| 13:27 | Bertl | make sure to have a space around operators and assignments, e.g. logic:='Z'; -> logic := 'Z';
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| 13:28 | manas | Ok I am on it...replying you as soon as it is completed
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| 13:29 | Bertl | make sure to avoid unnecessary brackets, e.g. if(count>=0) then -> if count >= 0 then
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| 13:29 | manas | Okay , point noted
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| 13:29 | Bertl | use well defined macros which make the code more readable, e.g.: if clk'event and clk='1' then -> if rising_edge(clk) then
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| 13:30 | Bertl | you can, and probably should use a 4 space indentation instead of 8 spaces to keep the code within 80 characters
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| 13:31 | Bertl | keep indentation of block structures aligned, e.g. case/end case (on the same indentation level)
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| 13:33 | manas | Thats to point them out...I am working on it
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| 13:34 | Bertl | also make sure to add your copyright and put the files under a FOSS license
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| 13:35 | manas | Okay
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| 14:14 | Kjetil | Can you explain why you are driving SDA high in the read address state?
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| 14:16 | manas | Kjetil: To send an ack bit to the master
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| 14:20 | Kjetil | what if there is another slave on the bus the matches the requested address? Which will want to signal ACK (driving the bus low)
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| 14:26 | manas | The 7 bit address for each i2c slave register is a unique one so there will at max one slave address that will match
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| 14:27 | Bertl | what Kjetil tries to hint here is that the IIC bus is an open drain bus system
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| 14:28 | Bertl | i.e. you never actively put power (e.g. a '1') on the bus
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| 14:28 | Bertl | you either pull down SCL or SDA or you leave it 'flowting' (the pullups take care of the '1')
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| 14:30 | manas | A error from my side apologies...I am correcting that
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| 14:31 | Bertl | (see https://en.wikipedia.org/wiki/I%C2%B2C, http://www.ti.com/lit/an/slva704/slva704.pdf and https://www.nxp.com/docs/en/user-guide/UM10204.pdf for more details on I2C)
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| 14:32 | manas | Thank you I will correct that immedeately
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| 14:36 | Bertl | you're welcome!
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| 14:51 | manas | Commit the changes, made the changes in the code indentation and sda line floating as mentioned
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| 14:53 | Bertl | what's line 34/35?
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| 14:55 | Bertl | check code style for line 36, 62, 67, 89 and indentation for 93, 105-119, 126 and more
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| 14:56 | Bertl | also still missing a copyright notice and license
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| 14:59 | manas | That was my silly mistake Adding the copyright notice and license
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| 15:02 | Kjetil | hm.. I wonder what an expression requiring the falling edge of two clocks at the same time will syntesize to
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| 15:08 | manas | Kjetil: Sorry but do you mean why i used the falling edge of SDA and simultaneously checked for the scl to be high or not...Well its the start condition
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| 15:09 | manas | If you are asking why I used clk edge and other falling edges then its to execute the process for every clk event
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| 15:09 | manas | To do tasks such as changing the state etc.
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| 15:10 | Kjetil | nah. You have the entire statemachine driven by the rising edge of the system clock, and I genuinly wonder how the FPGA will work when you have a rising_edge/falling_edge primitive inside there that checks a asynchronous clock
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| 15:20 | se6astian | changed nick to: se6astian|away
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| 15:25 | manas | The state machine runs on the system clock but the data/address read operation is done through the edge-event of the scl line...As the synchronization of the clocks is concerned, the change of SCL line should be along with edge change of the system clock
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| 15:26 | Bertl | which is something you cannot assume with I2C
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| 15:26 | Bertl | at any time there could be clock stretching on SCL for example
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| 15:29 | Kjetil | I guess you might get a FF on the SCL line and the data outsignal from that will be used as a clock in the next FFs
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| 15:30 | Bertl | which means that when the 'system' clock is (much) higher than the expected SCL clock, you can use (over)sampling to detect transitions
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| 15:32 | Kjetil | With at edge driven implementation the meta stable region will be an issue when the 'system' clock is fast compared to the i2c clock
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| 15:35 | manas | Okay so the idea is to implement the clock of the I2C using SCL line only?
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| 15:36 | Bertl | that would certainly work for the i2c slave but pose some serious challenges for the PWM side
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| 15:37 | Bertl | of course, nothing you couldn't handle with synchronization
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| 15:37 | Bertl | but I would rather suggest to sample SCL with your system clock and act based on changes there
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| 15:43 | manas | So using a clock_divider to sample out the system clock to the clock of desired frequency (ie, max 400KHz) will rather be a better option?
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| 15:45 | Bertl | not sure what you're trying to say, but you cannot make any assumptions on SCL except that it will be below 1MHz (400kHz)
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| 15:46 | Bertl | the IIC master decides when SCL will go low and for how long (i.e. that's out of your control for the I2C/PWM task)
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| 15:56 | manas | I will look into this problem and will reply you soon enough.
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| 15:56 | manas | Thank you for guidane
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| 15:57 | Bertl | no problem!
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| 16:17 | Kjetil | manas: you might want to add spike supression "required" for fast-mode i2c in UM10204
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| 16:48 | manas | Did the changes , now the I2C runs only the scl clock and not the system clock and data transfer takes place to pwm controller which is running on system clock. Made a branch and a copyright GNU GPL license Link : https://github.com/Manas173/PWM-generator-and-I2C_slave/tree/add-license-1
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| 16:48 | manas | Kjetil : I am looking into that matter
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| 17:05 | manas | Kjetil and Bertl : I will about it very soon Thanks for guidance
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| 17:06 | manas | *I will discuss about it very soon Thanks for guidance
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| 17:06 | Bertl | you're welcome!
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| 17:06 | manas | Good night
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| 17:13 | manas | Licensed both the master and a new branch : https://github.com/Manas173/PWM-generator-and-I2C_slave/tree/branch-1 Sorry the above was deleted
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| 17:39 | Bertl | off for now ... bbl
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| 20:45 | se6astian | off to bed
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| 20:45 | se6astian | good night
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| 21:36 | Davelister | good night people
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