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#apertus IRC Channel Logs

2018/01/28

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00:13
Bertl_oO
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Davelister
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Niels_so
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09:46
Niels_so
Good morning
09:48
se6astian
hi Niels_so
09:50
Rex0r
Hey Dave.
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Niels_so
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BAndiT1983|away
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Guillaume_Chooks
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Guillaume_Chooks
Hi everybody ! Hi Dave, you can contact me at guillaume(at)chooksprod.com if you want, i'm a french near Annecy. If we organize a maker faire in Lyon it will be good to be a group to know the camera. if it's sound interesting for you !
11:47
Guillaume_Chooks
I'm working for now but d'ont hesitate to contact me !
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BAndiT1983
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BAndiT1983|away
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joy_
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12:42
joy_
Hello
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joy_
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joy_
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12:45
joy_
Is anyone here? I am interested on USB interface using FPGA project where should I start?
12:46
se6astian
hi joy_!
12:47
se6astian
if you want to apply for GSoC for this task the best starting point is completing the FPGA/VHDL challenge: https://lab.apertus.org/T871
12:49
joy_
Thank you very much...As soon I complete one of the task what should I do then
12:50
Bertl_zZ
changed nick to: Bertl
12:51
Bertl
morning folks!
12:51
Niels_so
Hi Bertl
12:52
joy_
Hello I think you are the proposed mentor of the FPGA projects
12:52
Bertl
you are correct about that :)
12:53
Bertl
make sure to deliver clean code (T871) which uses a coding style similar to the exitsting VHDL code
12:53
Bertl
note: you can also do more than one of the qualification tasks (if you feel like it)
12:54
Bertl
that together with the application for GSoC will be the basis for our selection
12:55
Bertl
do not hesitate to ask if you have any questions
12:56
joy_
Please help me out what should I learn/ do after completing the task
12:59
Bertl
when you are finished with the qualification task(s), it is probably a good idea to make yourself comfortable with the hardware (online documentation, asking here, etc) and the task you are interested in (USB interface)
13:00
Rex0r
See links to reading here - https://wiki.apertus.org/index.php/GSoC_Overview
13:02
joy_
Thank you I will contact if I face any problem
13:02
Bertl
please do so and have fun!
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13:08
Niels_so
Bertl: is completing the GSoC mandatory? Or can I contribute on FPGA tasks without?
13:09
Bertl
nothing is mandatory, you can always contribute/work on anything you like
13:09
Niels_so
ok, thank you :-)
13:12
Bertl
no problem
13:13
Niels_so
Bertl: are the FPGA chosen for a given task following this rule: Zynq for image and high-speed signals processing, Lattice for signal conversion/low-area IPs?
13:13
Niels_so
(just wondering, that's something I see on some projects as well)
13:13
BAndiT1983
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13:15
manas
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13:15
manas
Hello
13:16
Bertl
hello manas!
13:16
manas
Was the code sent good enough?
13:16
Bertl
I haven't checked it yet, but I will do so shortly
13:16
manas
I was planning to complete one more task...
13:17
Bertl
you are definitely ahead of GSoC :)
13:17
manas
Thank you
13:18
Bertl
note: having more than one qualification task is nice, but handing in a perfect one is way better
13:19
Bertl
so make sure to use proper coding style, think twice about all your decisions, if necessary, start from scratch based on the ideas you gathered on the previous attempt, etc
13:19
Bertl
in short, it is more about quality than quantity
13:20
manas
Point noted....I will check the I2C code again and remake it if needed
13:21
Bertl
I know that we do not have a coding style guide (yet) but you can always ask me if something is unclear
13:22
Bertl
hint here: writing a coding style guide might be something worth doing (benefits the project and helps you understand it at the same time)
13:23
se6astian
(2:13:09 PM) Niels_so: Bertl: are the FPGA chosen for a given task following this rule: Zynq for image and high-speed signals processing, Lattice for signal conversion/low-area IPs? <- yes thats also our approach, correct me if I am wrong, Bertl
13:24
Bertl
indeed, we selected the FPGAs based on how nicely they fit the purpose
13:25
manas
Bertyl : Regarding the I2C: apart from sda and SCL I have used a clock (system clock)of frequency 100 MHz...
13:25
Bertl
Zynq was kind of given as back then the MicroZed was the only affordable (well documented) development board with enough I/Os
13:26
Bertl
manas: that's fine, some kind of system clock will always be present, just make sure that there are no problems with synchronization/clock domain crossings
13:28
manas
So Should I also implement a frequency divider as I know that I2C works on max 400 KHz...Or the SCL will be of max 400KHz frequency
13:29
manas
That is, the frequency given from the master by the SCL line will be of 400Hz right? So should bother of the system clock frequency divider?
13:29
Bertl
I'm looking at your code right now, first thing I see there is that you want to work on your indentation
13:29
Niels_so
se6astian, Bertl : ok, thank you. Have a good afternonn!
13:29
Bertl
you too!
13:29
Niels_so
afternoon*
13:29
Niels_so
thanks!
13:30
Bertl
manas: no, the master can use anything below 1MHz (or 400kHz)
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Niels_so
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BAndiT1983|away
changed nick to: BAndiT1983
13:35
manas
Okay so as the master has the control on SCL and SDA lines the frequency of the system clock in the code need not be changed..
13:39
manas
I will work on the code indentation and provide you a clean code in the future
13:39
manas
Thank you
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manas
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manas
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13:40
manas
Beryl: Please let me know if there is any error in the code
13:41
manas
I am sorry Bertl:
13:41
Bertl
yes, will go through the code tonight and provide some feedback
13:42
Bertl
it is a good idea to check here on a regular basis
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BAndiT1983
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BAndiT1983|away
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manas
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manas
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14:23
manas
Bertl : Sorry for late reply. I will surely visit here frequently
14:23
manas
Made some changes in the code indentation and added comments
14:25
Bertl
URL for the changes?
14:26
Bertl
https://raw.githubusercontent.com/Manas173/PWM-generator-and-I2C_slave/master/i2c_slave_pwm_control.vhd ?
14:26
manas
Yes correct
14:27
Bertl
here some input on that (indentation and other things):
14:27
Bertl
make sure to have a space around operators and assignments, e.g. logic:='Z'; -> logic := 'Z';
14:28
manas
Ok I am on it...replying you as soon as it is completed
14:29
Bertl
make sure to avoid unnecessary brackets, e.g. if(count>=0) then -> if count >= 0 then
14:29
manas
Okay , point noted
14:29
Bertl
use well defined macros which make the code more readable, e.g.: if clk'event and clk='1' then -> if rising_edge(clk) then
14:30
Bertl
you can, and probably should use a 4 space indentation instead of 8 spaces to keep the code within 80 characters
14:31
Bertl
keep indentation of block structures aligned, e.g. case/end case (on the same indentation level)
14:33
manas
Thats to point them out...I am working on it
14:34
Bertl
also make sure to add your copyright and put the files under a FOSS license
14:35
manas
Okay
15:14
Kjetil
Can you explain why you are driving SDA high in the read address state?
15:15
BAndiT1983
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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15:16
manas
Kjetil: To send an ack bit to the master
15:20
Kjetil
what if there is another slave on the bus the matches the requested address? Which will want to signal ACK (driving the bus low)
15:26
manas
The 7 bit address for each i2c slave register is a unique one so there will at max one slave address that will match
15:27
Bertl
what Kjetil tries to hint here is that the IIC bus is an open drain bus system
15:28
Bertl
i.e. you never actively put power (e.g. a '1') on the bus
15:28
Bertl
you either pull down SCL or SDA or you leave it 'flowting' (the pullups take care of the '1')
15:30
manas
A error from my side apologies...I am correcting that
15:31
Bertl
(see https://en.wikipedia.org/wiki/I%C2%B2C, http://www.ti.com/lit/an/slva704/slva704.pdf and https://www.nxp.com/docs/en/user-guide/UM10204.pdf for more details on I2C)
15:32
manas
Thank you I will correct that immedeately
15:36
Bertl
you're welcome!
15:51
manas
Commit the changes, made the changes in the code indentation and sda line floating as mentioned
15:53
Bertl
what's line 34/35?
15:55
Bertl
check code style for line 36, 62, 67, 89 and indentation for 93, 105-119, 126 and more
15:56
Bertl
also still missing a copyright notice and license
15:59
manas
That was my silly mistake Adding the copyright notice and license
16:02
Kjetil
hm.. I wonder what an expression requiring the falling edge of two clocks at the same time will syntesize to
16:08
manas
Kjetil: Sorry but do you mean why i used the falling edge of SDA and simultaneously checked for the scl to be high or not...Well its the start condition
16:09
manas
If you are asking why I used clk edge and other falling edges then its to execute the process for every clk event
16:09
manas
To do tasks such as changing the state etc.
16:10
Kjetil
nah. You have the entire statemachine driven by the rising edge of the system clock, and I genuinly wonder how the FPGA will work when you have a rising_edge/falling_edge primitive inside there that checks a asynchronous clock
16:20
se6astian
changed nick to: se6astian|away
16:25
manas
The state machine runs on the system clock but the data/address read operation is done through the edge-event of the scl line...As the synchronization of the clocks is concerned, the change of SCL line should be along with edge change of the system clock
16:26
Bertl
which is something you cannot assume with I2C
16:26
Bertl
at any time there could be clock stretching on SCL for example
16:29
Kjetil
I guess you might get a FF on the SCL line and the data outsignal from that will be used as a clock in the next FFs
16:30
Bertl
which means that when the 'system' clock is (much) higher than the expected SCL clock, you can use (over)sampling to detect transitions
16:32
Kjetil
With at edge driven implementation the meta stable region will be an issue when the 'system' clock is fast compared to the i2c clock
16:35
manas
Okay so the idea is to implement the clock of the I2C using SCL line only?
16:36
Bertl
that would certainly work for the i2c slave but pose some serious challenges for the PWM side
16:37
Bertl
of course, nothing you couldn't handle with synchronization
16:37
Bertl
but I would rather suggest to sample SCL with your system clock and act based on changes there
16:43
manas
So using a clock_divider to sample out the system clock to the clock of desired frequency (ie, max 400KHz) will rather be a better option?
16:45
Bertl
not sure what you're trying to say, but you cannot make any assumptions on SCL except that it will be below 1MHz (400kHz)
16:46
Bertl
the IIC master decides when SCL will go low and for how long (i.e. that's out of your control for the I2C/PWM task)
16:56
manas
I will look into this problem and will reply you soon enough.
16:56
manas
Thank you for guidane
16:57
Bertl
no problem!
17:17
Kjetil
manas: you might want to add spike supression "required" for fast-mode i2c in UM10204
17:48
manas
Did the changes , now the I2C runs only the scl clock and not the system clock and data transfer takes place to pwm controller which is running on system clock. Made a branch and a copyright GNU GPL license Link : https://github.com/Manas173/PWM-generator-and-I2C_slave/tree/add-license-1
17:48
manas
Kjetil : I am looking into that matter
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BAndiT1983
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18:05
manas
Kjetil and Bertl : I will about it very soon Thanks for guidance
18:06
manas
*I will discuss about it very soon Thanks for guidance
18:06
Bertl
you're welcome!
18:06
manas
Good night
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manas
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manas
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18:13
manas
Licensed both the master and a new branch : https://github.com/Manas173/PWM-generator-and-I2C_slave/tree/branch-1 Sorry the above was deleted
18:13
manas
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18:39
Bertl
off for now ... bbl
18:39
Bertl
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se6astian|away
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BAndiT1983
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se6astian
off to bed
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se6astian
good night
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se6astian
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22:36
Davelister
good night people
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