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#apertus IRC Channel Logs

2018/04/27

Timezone: UTC


01:22
rton
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RexOrCine
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ArunM
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ArunM
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05:36
Bertl_oO
off to bed now ... have a good one everyone!
05:36
Bertl_oO
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05:37
g3gg0
o.O
05:37
g3gg0
n8
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g3gg0
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ymc98
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se6astian|away
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07:10
se6astian
good day
07:48
RexOrCine|away
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07:53
ymc98
Bertl : I have a few questions. What must be the specifications of the packet? What is the format of the incoming data? Should the protocol be synchronous or asynchronous? How many peripherals would be connected to the lattice fpgas in a general use case? What encoding technique is best suited for our needs? What are the objectives for the first evaluation?
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sebix
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rton
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10:52
BAndiT1983|away
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11:06
Bertl_zZ
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11:06
Bertl
morning folks!
11:09
Bertl
ymc98: it is part of the task to find an 'optimal' solution for the packet protocol
11:10
Bertl
but we can do a brain storming to find some clues and to figure out some limiting parameters
11:11
Bertl
for example, a typical use case is a CSO attached to the AXIOM Beta as well as a bunch of Plugins and Shields which need to be configured and controlled
11:12
Bertl
for the encoding side, most likely an 8/10 code would be a good start for the low level transfer ... some kind of checksum/error correction might be required on top of that
11:15
BAndiT1983
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11:17
Bertl
regarding the first evaluation, you listed 'protocol design', MachXO2 SerDes, various communication tests between MachXO2 and Zynq as well as preliminary protocol implementation in HDL in your application
11:20
Bertl
realistically I do not expect 'the protocol' to be complete at the first evaluation but I expect to see working bidirectional communication between MachXO2 and Zynq with some instrumentation/measurements (e.g. error rate counter, bandwidth, latency) and a rough plan how the final protocol is going to work
11:27
RexOrCine
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11:46
ymc98
What would encompass bidirectional communication between MachXO2 and Zynq ( what communication protocol must we employ first )? For the rough plan for the protocol we must realize the worst case scenario ( a stress test of some sorts ) and design accordingly right?
11:53
ymc98
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12:18
Bertl
the lowest level will require bit and word synchronization between Zynq and MachXO (i.e. sync up the SerDes on both sides) to get a stable stream of data flowing
12:19
Bertl
and yes, I agree, we have to design for the worst case scenario, but only for the 'real time' portion of the protocol
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RexOrCine|away
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nmdis1999
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BAndiT1983|away
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nmdis1999
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se6astian
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16:36
Bertl
off for now ... bbl
16:36
Bertl
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17:05
sebix
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17:57
RexOrCine
OK. The first power board took 3 hours to get to a reasonable standard. So, yes, in theory I could have the other four done by monday.
18:03
se6astian|away
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g3gg0
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BAndiT1983
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20:18
TofuLynx
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20:19
TofuLynx
Hello!
20:19
g3gg0
hi
20:33
Bertl_oO
RexOrCine: great!
20:49
RexOrCine
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se6astian
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RexOrCine|away
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23:05
TofuLynx
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