Current Server Time: 04:53 (Central Europe)

#apertus IRC Channel Logs

2020/03/27

Timezone: UTC


23:05
electropositron
joined the channel
23:12
electropositron
left the channel
00:48
Bertl_oO
off to bed now ... have a good one everyone!
00:48
Bertl_oO
changed nick to: Bertl_zZ
01:55
CandyWendy
joined the channel
01:58
CandyWendy
left the channel
02:36
Spirit532
left the channel
02:41
Spirit532
joined the channel
05:03
Wanderer_99
joined the channel
05:24
BAndiT1983|away
changed nick to: BAndiT1983
05:27
Wanderer_99
left the channel
06:11
bluez_[m]
Good morning everyone! Sorry Bertl I fell asleep yesterday ':D
06:12
bluez_[m]
> bluez_: looks good, maybe add your IRC nick as well :)
06:12
bluez_[m]
Oh I forgot to add that... will do... thanks!!
06:19
BAndiT1983
changed nick to: BAndiT1983|away
07:00
Shashwat
joined the channel
07:01
Bertl_zZ
changed nick to: Bertl
07:02
Bertl
morning folks!
07:53
Wanderer_99
joined the channel
08:49
Shashwat
left the channel
09:27
Shashwat
joined the channel
09:56
omar31
joined the channel
10:20
Wanderer_99
left the channel
10:22
BAndiT1983|away
changed nick to: BAndiT1983
10:23
preetimenghwani[
Hello bertl
10:23
preetimenghwani[
Can you provide me the link where i can read about the current memory storage and repacking.
10:27
Bertl
there is some general information here: https://wiki.apertus.org/index.php/AXIOM_Beta/Manual
10:29
Bertl
and you can dig into the HDL for the remapper here: https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/peripherals/soc_main/pixel_remap.vhd
10:29
Bertl
note that the remapper only does the remapping not the packing, this happens in the top.vhd
10:35
preetimenghwani[
I actually had this confusion so for the task we dont have to perform repacking?
10:39
preetimenghwani[
Sorry for silly questions
10:43
Bertl
nothing to be sorry about
10:43
Bertl
the idea behind the 'new' remapper is to handle both
10:43
Bertl
i.e. reorder the pixels in such way that the follow certain rules
10:44
Bertl
and pack them into words which can be easily written to DDR memory
10:44
Bertl
note that these two can be separate units
11:07
Shashwat
left the channel
11:19
Shashwat
joined the channel
11:24
RexOrCine
joined the channel
12:05
preetimenghwani[
Okay thanks a lot Bertl :)
12:05
Bertl
np
12:29
Shashwat
left the channel
12:45
Wanderer_99
joined the channel
12:47
Wanderer_99
Here is my old unanswered question what sort of serdes are we supposed to implement for t871 task 1?
12:47
Wanderer_99
Parallel clock, embedded clock, 8b/10b?
12:52
Bertl
Task 1 assumes a clock with fixed phase relation, so no clock recovery
12:53
Bertl
also, there is no coding mentioned there, so no 8b/10b (which would be hard to do with 10/12bit anyway)
12:56
Bertl
off for now ... bbl
12:56
Bertl
changed nick to: Bertl_oO
13:29
BellaRebella
joined the channel
13:31
electropositron
joined the channel
13:33
BellaRebella
left the channel
15:26
schmoggie
okay, got two logic analyzers on route and a nex7 and various lenses for cheap
15:26
schmoggie
analysing can being
15:26
schmoggie
s/being/begin/g
15:32
BAndiT1983
schmoggie: nice, looking forward to it
16:07
Wanderer_99
left the channel
16:11
se6ast1an
schmoggie: excellent!
16:18
RexOrCine1
joined the channel
16:19
RexOrCine
left the channel
16:53
GabbyWest
joined the channel
16:53
Shashwat
joined the channel
16:54
apurvan
joined the channel
16:56
apurvan
left the channel
16:56
GabbyWest
left the channel
17:08
Shashwat
left the channel
17:40
Shashwat
joined the channel
18:01
YanetGarcia
joined the channel
18:04
YanetGarcia
left the channel
18:18
omar31
left the channel
18:30
Shashwat
left the channel
19:44
megora
joined the channel
20:08
megora
left the channel
20:08
megora
joined the channel
22:08
RexOrCine1
left the channel
22:09
BAndiT1983
changed nick to: BAndiT1983|away