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#apertus IRC Channel Logs

2019/07/26

Timezone: UTC


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04:33
Bertl_oO
off to bed now ... have a good one everyone!
04:33
Bertl_oO
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11:19
Bertl_zZ
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11:19
Bertl
morning folks!
11:20
apurvanandan[m]
Good morning
11:24
Bertl
hey apurvanandan[m], how is it going?
11:27
apurvanandan[m]
I found that the even the clock is not being received properly, if I change the data tranfer format. I am trying to find do the reset synchronization of DDRX4 without the soft IP rx_sync, as the problem is with that only
11:28
apurvanandan[m]
When I set the eclksynca stop signal to zero that data reception got correct
11:28
apurvanandan[m]
* on PAR simulation
11:29
apurvanandan[m]
But the eclksynca stop need to high generated for reset synchronisation.
11:32
Bertl
well, TN1203 says about ECLKSYNC:
11:32
Bertl
... can also be used to dynamically disable an edge clock to save power during operation
11:34
apurvanandan[m]
See page 33 of TN1203
11:34
apurvanandan[m]
Please see*
11:37
Bertl
well, the reset sequence 11-32 makes sense to me
11:37
Bertl
if you keep RX_STOP high, no edge clock can be expected
11:38
apurvanandan[m]
So thats what I am trying to implement right now
11:38
Bertl
so you didn't do any reset synchronization yet
11:39
apurvanandan[m]
I used RX_SYNC soft IP core given by Diamond
11:39
Bertl
which didn't work (not even in simulation), yes?
11:40
apurvanandan[m]
When I simulated only the machXO2 , it worked very fine, but simulating both fpgas together it doesn't
11:41
apurvanandan[m]
You see it worked good for ABABAB types data
11:41
apurvanandan[m]
on hardware too
11:42
Bertl
so you only simulated it with this kind of data (MachXO2 only)
11:43
Bertl
or does it still work when simulating the MachXO2 side only but with complex serial data?
11:43
apurvanandan[m]
When simulating with only machXO2 it works with al kinds of data in par simulation
11:43
Bertl
and the serial data is identical in both cases (MachXO2 only and both sides)?
11:44
apurvanandan[m]
Yes
11:44
Bertl
then your simulator must be broken
11:44
apurvanandan[m]
I also doubt in it :/
11:45
apurvanandan[m]
Some code doesn't work on simulation but works on hardware
11:45
Bertl
like for example?
11:45
apurvanandan[m]
The ABCDABCD types data works on hardware but not on simulation
11:46
Bertl
and you are doing post implementation simulation with timing annotation, yes?
11:46
apurvanandan[m]
Yup
11:47
aSobhy
morning Bertl
11:47
Bertl
aSobhy: morning! how is it going on your end?
11:49
aSobhy
I have a question and doubt
11:50
aSobhy
the doubt I'll use a pin from the PIC to reset the MachXO2, is that right ?
11:51
Bertl
why is it a doubt?
11:52
aSobhy
the question Is where is the shared clock input pin?, I'm lost in the scheme
11:52
Bertl
the PIC for RFW is called U2
11:53
Bertl
besides connecting the JTAG (TDO,TDI,TCK,TMS)
11:53
Bertl
it also has JTAGENB, PROGRAMN, INITN and DONE connected
11:54
Bertl
there are some more FPGA pins connected to the PIC and one pin is shared between MAchXO2, ZYNQ and PIC
11:54
Bertl
for RFW it is BANK13_SE_0
11:55
Bertl
for RFE (similar PIC connections), it is JX1_SE_0
11:56
Bertl
(connected to PT12A on each MachXO2)
11:58
aSobhy
so I can make BANK13_SE_0 to reset the two FPGA (ZYNQ & MachXO2)
12:01
Bertl
you can use BANK13_SE_0 as direct connection between ZYNQ and RFW
12:01
Bertl
and JX1_SE_0 for RFE
12:03
aSobhy
ah thats will be the clk sorry :)
12:07
Bertl
np
12:14
apurvanandan[m]
Bertl: As there it is mentioned that for stopping ECLKSYNCA we can use any clock that is slower than it
12:15
apurvanandan[m]
So can it be a from different clock domain?
12:17
Bertl
if it says 'any clock that is slower' then yes, but where do you read that?
12:18
apurvanandan[m]
Page 11-24
12:18
apurvanandan[m]
on TN1203
12:18
apurvanandan[m]
The footnote of clk_s signal
12:19
apurvanandan[m]
It is the input clock for RX_SYNC soft IP
12:19
Bertl
any slow clock refers to any 'slow' clock used in the block
12:19
apurvanandan[m]
So I can use internal oscillator?
12:20
apurvanandan[m]
Also divide by 2 of eclk with be fine
12:20
apurvanandan[m]
?
12:21
Bertl
I wouldn't choose a clock with no relation to eclk, but any divided down version should be fine
12:22
apurvanandan[m]
Yeah, I also have done the same.
12:24
Bertl
but it might as well be that the reset is completely asynchronous, and just needs to be held for at least 2 ECLK cycles
12:25
Bertl
well, not the reset, the delay after
12:25
apurvanandan[m]
The divided word clock ie sclk is also getting wrong when I change data pattern to ABCD
12:27
Bertl
did you test with a simple DDR x1 setup?
12:28
Bertl
no magic generators or Lattice IP :)
12:29
apurvanandan[m]
But how will I get 8 bit words, how will I do word alignment?
12:31
Bertl
how to get 8 or 10 bit from 2 bit parallel data?
12:31
apurvanandan[m]
Okay, the old way
12:37
apurvanandan[m]
Bertl: DDRX1 primitive is so simple :O , why didn't I used in first place
12:37
Bertl
because you never listen to me :)
12:37
apurvanandan[m]
facepalm
12:38
apurvanandan[m]
I will have full control of data after that
12:38
apurvanandan[m]
The alignment process and word generation
12:39
Bertl
the drawback, you won't be able to use that for higher frequencies/data rates
12:39
Bertl
because you are limited with the clock rate to process the data
12:39
apurvanandan[m]
Not at 300 MHz?
12:39
Bertl
we'll see
12:42
apurvanandan[m]
Well it is a challenge to make this gearing in 6 hours
12:42
apurvanandan[m]
I am doing that now
12:46
Bertl
well, you had almost two evaluation periods for that :)
12:46
apurvanandan[m]
:(
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15:19
aSobhy
Bertl when using the pin 88 to be the clock it gives an error in generating the bitstream file
15:20
Bertl
what kind of error?
15:20
aSobhy
I think that error because the clock pin is at the bottom when I try pin 34 it works
15:20
aSobhy
ERROR - netsanitycheck: The clock d_clk on comp clk_SYNC_INST port ECLKI is driven by general routing through comp Inst_DLLDELC. Please refer to 'Implementing High-Speed Interfaces with MachXO2 Devices'.
15:21
Bertl
so you probably want to feed that clock in a PLL first
15:22
Bertl
(or some clock routing element)
15:24
aSobhy
what routing elements ?
15:25
aSobhy
element*
15:26
aSobhy
I'll try pll
15:26
Bertl
e.g. the edge clock bridge
15:27
aSobhy
OK I'll search for it
15:28
Bertl
PLL is probably simpler and better anyway
15:28
Bertl
as you don't want to transfer high speed clocks over a single ended signal
15:29
Bertl
aSobhy, apurvanandan[m]: improptu meeting in one hour to discuss the current status
15:29
Bertl
(we'll open a separate channel for that)
15:30
apurvanandan[m]
Ok Bertl, Fine with me
15:32
aSobhy
OK Bertl
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19:12
Bertl
off for now ... bbl
19:12
Bertl
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