#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

Good morning

I found that the even the clock is not being received properly, if I change the data tranfer format. I am trying to find do the reset synchronization of DDRX4 without the soft IP rx_sync, as the problem is with that only

* on PAR simulation

well, TN1203 says about ECLKSYNC:

See page 33 of TN1203

well, the reset sequence 11-32 makes sense to me

So thats what I am trying to implement right now

I used RX_SYNC soft IP core given by Diamond

When I simulated only the machXO2 , it worked very fine, but simulating both fpgas together it doesn't

on hardware too

or does it still work when simulating the MachXO2 side only but with complex serial data?

and the serial data is identical in both cases (MachXO2 only and both sides)?

then your simulator must be broken

Some code doesn't work on simulation but works on hardware

The ABCDABCD types data works on hardware but not on simulation

Yup

aSobhy: morning! how is it going on your end?

the doubt I'll use a pin from the PIC to reset the MachXO2, is that right ?

the question Is where is the shared clock input pin?, I'm lost in the scheme

besides connecting the JTAG (TDO,TDI,TCK,TMS)

there are some more FPGA pins connected to the PIC and one pin is shared between MAchXO2, ZYNQ and PIC

for RFE (similar PIC connections), it is JX1_SE_0

so I can make BANK13_SE_0 to reset the two FPGA (ZYNQ & MachXO2)

and JX1_SE_0 for RFE

np

So can it be a from different clock domain?

Page 11-24

The footnote of clk_s signal

any slow clock refers to any 'slow' clock used in the block

Also divide by 2 of eclk with be fine

I wouldn't choose a clock with no relation to eclk, but any divided down version should be fine

but it might as well be that the reset is completely asynchronous, and just needs to be held for at least 2 ECLK cycles

The divided word clock ie sclk is also getting wrong when I change data pattern to ABCD

no magic generators or Lattice IP :)

how to get 8 or 10 bit from 2 bit parallel data?

Bertl: DDRX1 primitive is so simple :O , why didn't I used in first place

facepalm

The alignment process and word generation

because you are limited with the clock rate to process the data

we'll see

I am doing that now

:(

Bertl when using the pin 88 to be the clock it gives an error in generating the bitstream file

I think that error because the clock pin is at the bottom when I try pin 34 it works

so you probably want to feed that clock in a PLL first

what routing elements ?

I'll try pll

OK I'll search for it

as you don't want to transfer high speed clocks over a single ended signal

(we'll open a separate channel for that)

OK Bertl

off for now ... bbl