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#apertus IRC Channel Logs

2013/06/26

Timezone: UTC


02:26
dmj_nova
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02:26
dmj_nova
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08:05
se6astian
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11:04
Bertl
morning everyone!
11:19
dmj_nova
morning Bertl
11:20
dmj_nova
I need to get back on the apertus dev stuff
11:20
dmj_nova
spent most of yesterday either working on my moco rig project or practicing sketching
11:21
se6astian
hello!
11:21
dmj_nova
hi se6astian :)
11:21
se6astian
Stuart gave me some good feedback on the PCB parts I made so far
11:22
se6astian
now I need to redo most of it :)
11:22
se6astian
well not most of it...
11:22
dmj_nova
haha
11:22
dmj_nova
whew!
11:22
se6astian
but some parts
11:22
se6astian
nothing dramatic though
11:22
Bertl
how so?
11:22
se6astian
Here are some initial things I'm seeing.
11:22
se6astian
1. C2-C11 need to go next to the sensor pins they are closest to in the schematic. You'll need to populate them in the space you show as reserved for sensor cooling. They can go on the top or backside of the PCB. In all cases it's best to place them on the top layer since you want a direct connection to the sensor pin to avoid via inductance.
11:22
se6astian
2. I'm guessing that the cap re-positioning will also cause a change in your power plane.
11:22
se6astian
3. You'll need to clean up the LVDS traces starting from around R3/R4 and going up to the FMC connector. The right angle connection you have isn't going to work well. You want to space these trace pairs apart and provide ground fill between the LVDS pairs.
11:22
se6astian
4. Keep in mind that there is no bottom side silkscreen with ExpressPCB. You can remove it in the layout for the bottom side mounted components if you want.
11:22
se6astian
5. LVDS pairs still need to be spaced properly.
11:22
se6astian
6. It looks like C12-C30 could possibly move to the top side of the PCB. That would improve the capacitors performance since there wouldn't be via inductance (~1nH/via).
11:22
se6astian
7. I see a could sensor pins that you use one via to attach to two sensor pins. These need to be separate vias to reduce inductance and lower resistance to the power plane.
11:22
se6astian
8. Keep in mind that you'll need to do a copper fill on the top and bottom layers and attach the fill to ground through stitching vias all around the board's edge and throughout the PCB where ever possible.
11:24
se6astian
I figured out I can also place the SMT 0402 capacitors under the Andon socket on the top side
11:25
se6astian
as the andon socket has a model with "window"
11:26
Bertl
careful, if we want to cool the sensor somehow, you don't want any capacitors there
11:26
Bertl
but I haven't looked at the current layout yet, so that's just handwaving
11:27
dmj_nova
Good thing you had Stuart look at it and not me because I haven't done enough PCB stuff to have an intuition about where inductance issues will happen
11:29
se6astian
Bertl, true but I can place a few at the outher area of the sensor and we can try to cool it in the middle
11:30
dmj_nova
hmm, I would think you'd want the sensor to be evenly cooled
11:30
dmj_nova
unless you think it would have minimal impact on heat spreading
11:35
Bertl
I still haven't seen the socket (i.e. we have too little information there) to consider cooling
11:35
Bertl
we probably need (guessing) something to bridge the gap between senson and PCB when using the socket (as the sensor can be soldered on as well)
11:36
Bertl
so it would require some kind of elastic heat conducting material
11:36
Bertl
which probably will ensure somewhat uniform heat distribution anyway
11:37
se6astian
I would cut a hole into the PCB behind the sensor and attach a metal to the sensor from behind with heat conducting paste
11:37
se6astian
and attach a heatsink to that metal
11:41
Bertl
I'll comment on that when I have more information :)
11:42
Bertl
(usually directly attached heatsinks require almost perfect alignment and good contact, and usually are a bad choice for anything which can break because they tend to cause mechanical stress)
11:44
se6astian
cant a heat conducting paste close the gap without any mechanical stress?
11:45
Bertl
sure, but it also reduces the amount of heat which can be dissipated
11:46
Bertl
maybe a number of holes and a slow turning fan might be a good choice, maybe heat transfer via PCB is the perfect solution ... as I said, not enough data atm :)
11:46
se6astian
maybe its better to drop the cooling idea? I mean we don't know if it will make any difference, if it will work at all and it makes the PCB layout a lot more difficult to leave a unusable area in the center of the sensor....
11:47
Bertl
maybe better postbone it, and if the layout allows for some holes to measure and/or cool, it's nice but if not, so what
11:47
Bertl
*postpone
11:57
se6astian
ok
11:58
se6astian
what data would satisfy you, holding a socket in hand?
12:00
Bertl
either that or a 3D model or a proper drawing which has all data
12:02
se6astian
I am afraid we wont get any other drawings than what they sent us so far, I just sent another email to inquiry their US based delivery
12:03
Bertl
when we get a sample or the first sockets, maybe you can put them on a high-res scanner for a start
12:07
se6astian
sure, we got some good flatbed scanners at the university
12:34
se6astian
LVDS pairs should be as close together to each other as possible right?
12:35
Bertl
yes
12:36
se6astian
so when stuart says: "manually adjust the spacing on the LVDS pairs as per the schematic note"
12:37
se6astian
and the schematic note, says: 10 mil trace, 6 mil space = 100 ohms
12:37
Bertl
then you want to keep that :)
12:37
se6astian
he means all LVDS traces should be 10mils and have 6 mil spacing between the pair right?
12:38
Bertl
for 100 ohm (not sure that is the design though)
12:38
se6astian
he also writes: 6 mil trace/space=117 ohms
12:38
se6astian
the LVDS traces he created are all 10 mil wide though
12:40
Bertl
which suggests that 100 Ohm is the target impedance for the differential pairs :)
12:41
se6astian
perfect
12:41
se6astian
then I think I know what to do
12:42
se6astian
he also suggested putting gnd traces between the pairs
12:42
se6astian
should they also be spaced 6mil to the LVDS traces
12:42
se6astian
or is that distance not relevant since its just a shielding?
12:42
Bertl
between different pairs, yes, not between the pair
12:43
Bertl
(the ground)
12:43
se6astian
yes
12:43
se6astian
like ||GND||GND||GND||
12:43
Bertl
does the design use microstrip or stripline?
12:43
se6astian
good question, how do I find out? ;)
12:43
Bertl
do you have ground planes below/above the pairs?
12:44
se6astian
its a 4 layer board: top/gnd/power/bottom
12:44
se6astian
LVDS pairs are both on top and bottom
12:45
Bertl
http://www.ewh.ieee.org/r5/denver/rockymountainemc/archive/2000/diffimp.pdf
12:45
Bertl
(just a little reading)
12:47
Bertl
so basically you are doing microstrip, i.e. below the signals is a ground/power layer and the signals themselves are on the outside of the board
12:47
Bertl
http://en.wikipedia.org/wiki/Microstrip
12:47
Bertl
http://en.wikipedia.org/wiki/Stripline
12:49
se6astian
Stuart wrote more notes on the schematics: 12 mil dielectrics on top-bottom, Dielectric constant: 4.6 +/-0.2
12:59
se6astian
ah I just noticed that expresspcb can do a filled GND plane automatically after all traces are done
13:02
jucar
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jucar
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13:26
jucar
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13:28
se6astian
so how are things going on your end?
13:28
Bertl
slow, but fine, I'm currently playing with the PL-PS interconnect
13:29
jucar
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13:29
Bertl
ah, btw, I uploaded a few simple examples for PL code (early work :)
13:29
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/blink*.vhd
13:30
Bertl
as usual, comments are welcome
13:37
se6astian
interesting
13:38
se6astian
btw, what do you think if we would use a higher model number for the full Axiom camera, it wouldnt be covered by the gratis webpack license anymore
13:38
se6astian
show stopper for open source project like us
13:38
se6astian
or can we find a workaround?
13:38
se6astian
*higher model Zynq
13:42
Bertl
I think: not a good idea to lock out the community :)
13:42
Bertl
but I'm not sure what the WebPack does or does not cover
13:43
Bertl
to me, it looks like the license only affects the GUI tools (as far as I can see) and probably the IP
13:46
se6astian
webpack covers the "lowest 3 zynq models", they are not very specifc at what they mean with that
13:46
se6astian
but I am afraid those are not the ones with GTX lanes
13:47
Bertl
probably not, that was my initial comment on the ML
13:48
se6astian
ah wait, Z-7030 is covered in webpack
13:50
se6astian
4 GTX with 6.6 (lower 2 package types) or 12 Gb/s (higher package type)
13:50
Bertl
yep, that seems to be the last one working with the tools
13:50
Bertl
(just verified with xflow)
13:51
se6astian
does xflow also specify which package types are supported? http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf
13:51
se6astian
or all of them?
13:52
Bertl
you are probably interested in the high pin count package
13:53
Bertl
it definitely supports the fbg676
13:53
se6astian
yes, like the FFG676
13:53
Bertl
let me check that one
13:54
Bertl
seems to work fine as well
13:57
se6astian
good!
13:57
se6astian
its more expensive though, 300-500$ on digikey
14:00
Bertl
well, the xc7z020 is already 200 USD there
14:01
Bertl
200-300 actually
14:02
Bertl
GTX would probably be required for high speed SDI or similar
14:03
se6astian
do you think the lower speed GTX models (4x 6.6Gb/s) could be enough?
14:04
se6astian
2x SDI, 2x SATA ?
14:04
Bertl
probably, still not sure that we want both at the same time
14:07
se6astian
if we make the separationg between recorder and camera block yes
14:07
se6astian
ok, but this is good news, I had the fear that we wouldn't be able to use the Zynq at all because of this license issue, but everything is good now :)
14:09
Bertl
usually the SDI stuff seems to use some kind of chaining
14:09
Bertl
i.e. camera => recorder => display
14:10
Bertl
so, not sure why we would want to output SDI _and_ record to SATA at full speed for example
14:10
Bertl
(at the same time, that is)
14:10
se6astian
yes and no
14:10
se6astian
a display would most likely have the OSD while the recorder should get a clean signal
14:11
se6astian
also the display doesnt need to get a 4K signal (FullHD is good enough), which the full featured recorder should get
14:12
Bertl
yeah, but the display would not require 4K @ 60fps :)
14:13
Bertl
so no need to go high bandwidth/raw there
14:13
Bertl
but I also think we should postpone this until we know more about the platform
14:14
Bertl
i.e. what the zynq can actually do
14:16
se6astian
agreed
14:18
Bertl
We should hang out. :)
14:20
se6astian
Google hangout?
14:20
Bertl
nah, I was more citing kung-fu-panda than actually suggesting to 'hang out'
14:21
Bertl
somehow the 'agreed.' reminded me :)
14:21
se6astian
ah ok :)
15:58
se6astian
LVDS routing question
15:58
se6astian
http://picpaste.com/around-we0hv8J8.jpg
15:59
se6astian
is it OK to interrupt the pair for a short distance to go around a via
15:59
se6astian
or better to keep them together and route booth around the via?
16:14
se6astian
Bertl? any ideas?
16:31
Bertl
sec, I just managed to get PS-PL interconnect to work properly
16:33
Bertl
no, you don't want to have a via between a pair
16:33
Bertl
where does that come from btw? nothing can be connected there
16:34
Bertl
in the case shown above, I'd simply route both connections above the via (if it is used for anything)
17:23
se6astian
thanks, will do that
17:23
se6astian
PS-PL interconnect, hurray!
17:24
Bertl
\o/
17:24
Bertl
somehow the documentation on the zynq is rather sparse
17:25
Bertl
or maybe I'm not looking in the right places, for example I'm still searching for a register description for slcr.LVL_SHFTR_EN
18:47
se6astian
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se6astian
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18:54
se6astian
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18:55
se6astian
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19:11
Bertl
I've uploaded the pl-ps example, I'll also upload an xmd script to initialize the PS registers shortly
19:11
Bertl
(if somebody is interested :)
19:38
Bertl
okay, the files are in the usual place: http://vserver.13thfloor.at/Stuff/AXIOM/
19:39
Bertl
blink_plps{.prj,.vhd,_init.tcl} and ps7_stub.vhd
19:40
se6astian
nice, I dont have a zedboard to test at the moment ;)
19:40
Bertl
any comments on the vhdl or process in general are welcome ...
19:40
se6astian
but I am very happy to see so much progress
19:40
se6astian
I am working on the PCB all day already
19:41
Bertl
next planned step is to utilize one of the PS components, in particular the I2C via PL
19:41
Bertl
I'm going to attach a simple sensor via Bertl-Hack-PMOD for this purpose :)
20:35
se6astian
Great, just commited V009 of the PCB and sent stuart an email