#apertus IRC Channel Logs

Read the article on heise about your project

hi Marco74, thats great

Actually English would not be the problem but I could also write German

Do you mind?

haha, griaß di :D

Naja, ein bisschen etwas über mich:

(Elektrotechnik/IT) in Innsbruck

war bis vor Kurzem auch Sysadmin in eine 40 Mann Firma, 3 sites, 2 Standorte

Programmieren:

embedded aber nicht

Wo habt ihr euer Labor?

sehr gut

Ich kann auch einmal vorbeikommen

Python hab' ich mir mehr oder weniger selber beigebracht

wenn du dir die weltreise antun willst gerne :)

Innsbruck – Wien sind 4:08 min

und da ist noch viel potential drin: Deutsches Eck bzw. Wallersee

hey Marco74, what area seems most interesting to you (regarding AXIOM Alpha or Beta)?

Actually developing would be interesting

I never did anything like embedded, but that would be very interesting

In school we had to write a software hiding information in a bitmap image

Median Blur, Sobel, etc.

just trying to get an idea what task might be interesting, challenging but still doable for now

humans only can realize a few

3 channels per pixel

This is only possible with bmp

I see, well, maybe you would like to play around with image processing then?

but actually bits and bytes are my world

well, maybe the following could be interesting to you:

ok, and image processing should happen inline as I asume

the first pipeline receives the sensor data and converts it to a 'proper' memory representation, doing some preprocessing like column/row noise correction and linearization, etc

now, I think it would be beneficial, if we could replicate the effects of those pipelines (they are VHDL code working inside the FPGA in realtime)

so basically one starts with a perfect 4k+ still image, then the code rasterizes it to simulate what the sensor will 'see'

the second part would then be to process this raw data in the same way the output pipeline does it in the FPGA, so you end up with a full HD frame which is basically what you would see on a monitor

sounds really interesting

bun actually I wasn't involved into the project,

of course

both pipelines exist and work in the AXIOM Alpha FPGA

or C++

of course

note that part of the processing is how the hardware works

so for example, the rasterization the sensor does isn't implemented anywhere (yet) it just happens

I asume

a 2d photo-sensor-array

that testing is easier

so for now we have that vhdl, further improvements would be done in C, therefore the port is needed?

so I really need to care about cpu-capacity and throughput time?

it won't hurt, but it isn't your main concern I guess

ah, ok

but I'd say that isn't the top priority

actually understanding VHDL could be quite difficult

this probably helps at this task

it is harder to get it right when you're designing new modules

so of course, it won't hurt to lear a little VHDL and FPGA design as well

I love learning new stuff

Just didn't have a project to learn VHDL for

if you really want to dig into VHDL, I suggest to get a really cheap FPGA development board (there are some with lower end FPGAs for 30-60 EUR)

or, alternatively, if you don't want to 'mess' with electronics, you can grab GHDL and play with that

i.e. VHDL doesn't require an FPGA per se

ah....

?

the cmv_hdmi2 is the current design

yes, there is a schematic overview of the pipelines, sec

thx.