Current Server Time: 06:09 (Central Europe)

#apertus IRC Channel Logs

2021/03/26

Timezone: UTC


00:41
Topic
apertus° - open source cinema | www.apertus.org | join the apertus° Lab: http://lab.apertus.org/ | IRC Logs available at: http://irc.apertus.org | Weekly IRC meeting: Monday 18:00 CET/CEST
00:41
se6ast1an
has set the topic
01:56
vnksnkr
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lexano
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lexano
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vnksnkr
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vnksnkr
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04:44
Bertl_oO
off to bed now ... have a good one everyone!
04:44
Bertl_oO
changed nick to: Bertl_zZ
05:27
BAndiT1983|away
changed nick to: BAndiT1983
05:37
mumptai
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06:50
se6ast1an
good day
06:53
BAndiT1983
hi
06:54
se6ast1an
how are things going?
06:55
cnu
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06:55
satacker[m]
hi , hope everyone is doing good
06:55
satacker[m]
I am a bit busy with college vivas
06:55
satacker[m]
Will get back on Task 2 and coding style soon
06:56
cnu
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06:59
se6ast1an
very good
07:10
fredy__
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fredy__
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bluez_
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WalterZimmermann
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illwieckz
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illwieckz
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11:27
Bertl_zZ
changed nick to: Bertl
11:27
Bertl
morning folks!
11:29
BAndiT1983
hi
11:34
markusengsner
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11:37
hp_dopeman[m]
Good morning
13:10
vnksnkr
hi
13:10
vnksnkr
I've tried my hand on the vhdl challenge task 2
13:11
vnksnkr
https://github.com/vnksnkr/UART-SPI-BRIDGE-VHDL
13:22
Bertl
you want to format and indent your code properly, currently it's more a rollercoaster ride ;)
13:25
Bertl
if rising_edge(SCK) then
13:25
Bertl
if (SSEL = '0') then
13:25
Bertl
if(r_bitcnt < 7) then
13:27
vnksnkr
oops :
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syung
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13:31
Bertl
note that these three lines contain not only indentation issues, but also white space and unnecessary parentheses
13:31
Bertl
*missing white space
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syung
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syung
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syung
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BAndiT1983
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mumptai
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BAndiT1983|away
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uberardy
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felix_
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markusengsner
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19:02
vnksnkr
I've fixed the indentation issues and removed the unwanted parantheses
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fredy__
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markusengsner
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