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#apertus IRC Channel Logs

2017/03/26

Timezone: UTC


00:00
Bertl_oO
yeah, I would reserve at least a few days for this
00:01
Bertl_oO
there will be a lot we learn from the actual implementation and it will require some discussion/brain storming what can be improved in the future
00:01
Bertl_oO
so maybe 2 or even 3 days
00:30
Elbehery__
Aha okay, i will include this in the sched.
00:31
Bertl_oO
excellent!
00:31
Elbehery__
Thanks so much for your time
00:31
Bertl_oO
you're welcome!
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01:48
Bertl_oO
welcome xeechou!
01:49
xeechou
hello
01:49
xeechou
I just compiled openCine on Arch
01:49
xeechou
But I don't know how to use it...
01:50
xeechou
there seems to be many buttons didn't get implemented
01:50
Bertl_oO
best check with BAndiT1983|away when he comes back
01:50
xeechou
okay, thanks
01:50
Bertl_oO
np
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06:04
Bertl_oO
off to bed now ... have a good one everyone!
06:04
Bertl_oO
changed nick to: Bertl_zZ
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07:26
anuditverma
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07:27
anuditverma
Good morning
07:29
anuditverma
Please review and comment on my first draft of the proposal so that I can improve it more https://docs.google.com/document/d/1kGqTBqHNRu6QBCnJ3S3Zgqod8BQ911QnNTKBaGmsdFg/edit
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09:34
onenot8
hey
09:39
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10:18
BAndiT1983|away
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10:39
niemand
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11:06
RexOrCine[m]
Morning folks.
11:07
BAndiT1983
hi
11:19
Bertl_zZ
changed nick to: Bertl
11:20
Bertl
morning folks!
11:20
BAndiT1983
hi
11:22
usmankhan
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11:22
usmankhan
Hello
11:23
usmankhan
I have completed an initial draft proposal: https://github.com/usmanwardag/gsoc17_proposal/blob/master/pid.pdf. I would appreciate any feedback or comments on this
11:24
usmankhan
Please note that I am still working on the appendix section. The rest of it is mostly complete
11:24
Bertl
will check it out shortly.
11:24
usmankhan
Thanks
11:31
RexOrCine[m]
It's well laid out.
11:33
usmankhan
Thanks, I had to change the file name, so proposal can now be found here: https://github.com/usmanwardag/gsoc17_proposal/blob/master/proposal.pdf
11:45
Bertl
anuditverma: looks good so far
11:46
Tanos
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11:47
Bertl
usmankhan: nice to see that you're using TeX for the document
11:54
Bertl
nitpick: in the introduction, you mention a single FET for the regulator, but in your schematic, you have the 'typical' two FETs for a synchronous buck where the diode is replaced by the second MOSFET
11:55
Bertl
s/output voltage of the sensor/output voltage for the sensor/
11:56
usmankhan
yes, correct
11:58
Bertl
as I suggested last time, you probably should extend the feedback block (in Fig 1) to include Vf and the OpAmp in+
11:59
Bertl
the reason for this is that strictly speaking you do not want to change Vf in the feedback block but you need to change in+ to create e.g. hysteresis
11:59
usmankhan
Yes, actually my plan is to create a detailed schematic (with calculations) in the Appendix. Once that is done, I will modify the main schematic as well
12:00
Bertl
okay
12:03
niemand
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12:03
Bertl
5.6 s/youll/you'll/
12:05
Bertl
btw, for a final syntactic and sematic check, it's probably best to talk with RexO or some other native English speaker ... I'm sure they will gladly check the document if you ask nicely
12:06
usmankhan
Ah, TeX ommitted that, I will correct it
12:06
usmankhan
Sure
12:07
Bertl
otherwise it looks good to me.
12:09
Bertl
personally I would add a paragraph about MOSFET selection to the Appendix, because that will also be critical for the switcher
12:09
usmankhan
Okay
12:12
Bertl
also check out what other GSoC applicants suggested (mostly here on IRC), maybe one or the other thing might be worth adding to your considerations
12:13
Bertl
like for example ADC vs comparator (we still have no clue if the ADC would be worth the trouble, space and I/Os)
12:13
Bertl
or the idea to use something different than a typical PID controller
12:17
usmankhan
Alright, I will look through the logs
12:21
Bertl
one more point which just came to my mind:
12:22
Bertl
we will have 8+ switchers on the power board (most likely implemented in a single FPGA) for the 8+ power rails
12:22
Bertl
so they need to be synchronized in such way, that they do not all draw power from the source at the same time
12:23
Bertl
otherwise there will be oscillation on the input rail
12:24
usmankhan
Right, I will discuss this in the proposal
12:27
Bertl
btw, Intersil has a number of nice documents regarding buck topologies and how to improve for certain conditions
12:28
Bertl
(Onsemi and Texas Instruments as well)
12:29
usmankhan
Yes, I followed one by Texas Instruments. I will see if I can find other resources
12:29
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12:51
BAndiT1983
Bertl, are maximum pf 2 parameters sufficient to set the registers of CMV? i know that gain required gain (of course) and ADC range, or can they be set separately?
12:52
BAndiT1983
if separetely is possible, then i could just provide 1 parameter, so it's simpler to process
12:52
Bertl
don't think that would be enough, the image regions are for example a lot more complex than that
12:53
Bertl
and binning/subsampling changes quite a number of registers too
12:53
BAndiT1983
i've planned also to provide possibility to set parameter as payload with length, in short byte array
12:54
BAndiT1983
most things will be enclosed in helper methods, it's just about boiling it down to required params
12:54
Bertl
in general it might be worth to keep a register shadow and update the registers with some kind of commit
12:54
BAndiT1983
ah, alright, so there should be a method like Commit() and Execute()
12:55
Bertl
i.e. let the user 'modify' registers in a buffer with separate commands (keep them simple)
12:55
Bertl
and then, update all the registers which have changed in one go, preferably synchronized to the image acquisition
12:57
Bertl
I thought about implementing this in the FPGA, which might be overkill but might also be a good idea to ensure that those changes happen at the right time
12:58
BAndiT1983
at the moment i write (at least theoretically, as it results in SEGFAULT on normal PC) to the mapped memory, do we need a separate one so FPGA transfers it at right time?
12:59
Bertl
the memory mapped cmv registers are a direct interface to the SPI bus
12:59
BAndiT1983
so the question is if we just use separate one, so you can trigger it at right time from logic
12:59
Bertl
so whatever you read will come directly from the sensor and what you write will be written immediately
13:00
Bertl
we might add a buffer/shadow in the FPGA at some point, which then would use some kind of 'special' register or register range to 'update' the registers
13:01
Bertl
haven't had time to think this through, but you can create a lab task for it so that I remember :)
13:01
BAndiT1983
alright will do :)
13:01
BAndiT1983
just want to set a plan beforehand, as gsoc is approaching
13:02
BAndiT1983
so the guys who do API task do not have a stall
13:05
BAndiT1983
task added, feel free to correct it, if it's not clear enough or wrong
13:05
BAndiT1983
https://lab.apertus.org/T767
13:05
Bertl
tx
13:05
BAndiT1983
i will proceed with client-server communication as it's essential, afterwards we can still adjust all the things till it's right
13:05
BAndiT1983
no problem, lab maintenance is important
13:06
Bertl
agreed
13:06
BAndiT1983
i hope our lab will be updated at some point to the newest version
13:07
BAndiT1983
you have to aggree, the newer one looks really sleek
13:07
BAndiT1983
https://secure.phabricator.com
13:07
Bertl
I'm certain it will
13:07
Bertl
doesn't look very different to me
13:08
BAndiT1983
you have to look deeper, many improvements
13:08
BAndiT1983
don't know if ours already has such infos -> https://secure.phabricator.com/T9893
13:08
BAndiT1983
git branching looks helpful, tags are a must for me
13:10
BAndiT1983
possibly that they just renamed/added the project assigning to tags
13:17
usmankhan
/quit
13:17
usmankhan
\quit
13:17
usmankhan
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13:42
Bertl
off for now ... bbl
13:42
Bertl
changed nick to: Bertl_oO
13:47
RexOrCine[m]
As far as I know admin was asked to update it over a month back.
13:50
BAndiT1983
Rex, you know that everything takes its time ;)
13:57
RexOrCine[m]
Aye, like sorting my phone out finally. You're right.
14:03
Bertl_oO
the problem is not the update itself, the problem is that our server is sooo outdated, that any update is a nightmare
14:04
Bertl_oO
(but this is worked on already)
14:05
BAndiT1983
what do you mean by outdated? linux not updated or hardware?
14:06
Bertl_oO
Linux
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se6astian|away
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15:37
RexOrCine[m]
If anyone reading is on Twitter could you give this a RT please - https://twitter.com/apertususer/status/844975692567793664
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BAndiT1983
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BAndiT1983|away
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se6astian
off to bed
21:56
se6astian
good night
21:56
Bertl_oO
nn
21:56
se6astian
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fredy
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BAndiT1983
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