#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

Morning!

The past few weeks I've been mostly passively reading up on AXI spec and DDR spec and the Zynq 7000 DDR controller, because I wanted to get to the bottom of why my framebuffer wasn't working. Now I think I have a good concept of just how naive the FIFO feeding was

in the meantime anuejn built a working linux framebuffer :)

Yeah, I checked my pings - wait, outright a linux framebuffer? As in a proper video driver renders stuff to it?

EmilJ: tx!

so you can get a tty on it

I see - so far I know little about linux. It's a gaping hole between my experiences of {working with RTOS and writing a trivial filesystem for a school project} and {running Debian}... I need to fix that

is this what you are referring to?

no

EmilJ: LOL, nice find

hmm, just checking: stride can be defined to be larger than size of format multiplied by width for DMA alignment or multi-resolution buffer reasons?

interesting, the AXI reader doesn't do bursts, I'm surprised. I think this would waste AXI and block the processor from accessing RAM via the DDR controller interface a lot - I'm working on figuring out to what degree this might be a problem to figure out just how many AXI clocks are going to have to be burned on bridges, interconnects, DDR controller arbitration, and actual DDR latency

I'd love to hear about that setup

this runs at a efficiency of nearly equal to the optimal efficiency ((16 data cycles) / (16 data cycles + 1 address cycle)) ~ 94`

you have to consider, that the zynq side has a large fifo and probably quite sophisticated transaction combining / pipelining / etc logic

EmilJ: I don't think we tested single word transactions for the writer, atleast I cannot recall the results

EmilJ: for the writer we were comparing sending the address independent from the data vs first sending the address and then all the data, before sending the next address

Ah, okay - so you were delaying WVALID in a burst transaction

https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/7370da1409d3532774fce4797d5e759a075bd7d2/src/lib/bus/axi/buffer_writer.py

1. do a address transaction

repeta

EmilJ: the axi reader currently doesnt do bursts mainly because of lazyness

we didnt do any benchmarking before doning design decisions on the reader

:)

by the way I'm confused about how the AXI reader has an output payload (that one ends up being None in the image_stream case right) as well as output out_of_band_signals

off for now ... bbl