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#apertus IRC Channel Logs

2020/11/25

Timezone: UTC


02:01
mumptai
left the channel
06:02
Bertl_oO
off to bed now ... have a good one everyone!
06:02
Bertl_oO
changed nick to: Bertl_zZ
08:00
LordVan
joined the channel
08:44
BAndiT1983|away
changed nick to: BAndiT1983
10:31
Bertl_zZ
changed nick to: Bertl
10:32
Bertl
morning folks!
10:52
EmilJ
Morning!
10:53
EmilJ
Sorry for disappearing for a bit. Had to catch up with school
10:54
EmilJ
The past few weeks I've been mostly passively reading up on AXI spec and DDR spec and the Zynq 7000 DDR controller, because I wanted to get to the bottom of why my framebuffer wasn't working. Now I think I have a good concept of just how naive the FIFO feeding was
10:55
vup
EmilJ: hi, welcome back
10:55
vup
in the meantime anuejn built a working linux framebuffer :)
10:55
EmilJ
BTW Bertl those are some fine solid copper bodges
10:55
EmilJ
Yeah, I checked my pings - wait, outright a linux framebuffer? As in a proper video driver renders stuff to it?
10:55
EmilJ
also hi vup
10:56
Bertl
EmilJ: tx!
10:56
vup
not really a video driver, but more the normal linux framebuffer subsystem
10:56
vup
so you can get a tty on it
10:56
vup
(linux has a generic memory mapped framebuffer driver)
10:58
EmilJ
I see - so far I know little about linux. It's a gaping hole between my experiences of {working with RTOS and writing a trivial filesystem for a school project} and {running Debian}... I need to fix that
10:58
EmilJ
https://wiki.osdev.org/Printing_To_Screen
10:58
EmilJ
is this what you are referring to?
10:59
EmilJ
> The text screen video memory for colour monitors resides at 0xB8000
10:59
vup
no
10:59
vup
this: https://en.wikipedia.org/wiki/Linux_framebuffer
10:59
Bertl
EmilJ: LOL, nice find
10:59
vup
using this: https://www.kernel.org/doc/Documentation/devicetree/bindings/display/simple-framebuffer.txt
11:09
EmilJ
hmm, just checking: stride can be defined to be larger than size of format multiplied by width for DMA alignment or multi-resolution buffer reasons?
11:14
vup
yes, I would assume so
12:20
BAndiT1983
changed nick to: BAndiT1983|away
13:44
BAndiT1983|away
changed nick to: BAndiT1983
14:03
EmilJ
interesting, the AXI reader doesn't do bursts, I'm surprised. I think this would waste AXI and block the processor from accessing RAM via the DDR controller interface a lot - I'm working on figuring out to what degree this might be a problem to figure out just how many AXI clocks are going to have to be burned on bridges, interconnects, DDR controller arbitration, and actual DDR latency
14:05
Bertl
well, the AXI reader used in the Axiom Beta does do burst reads but IIRC, vup/anuejn implemented their version without bursts after doing some benchmarks and getting comparable performance
14:11
EmilJ
I'd love to hear about that setup
14:13
vup
we only did extensive testing for the writer iirc, where the main difference was not doing out of order transactions ie only submitting a new address after having written the burst
14:14
vup
this runs at a efficiency of nearly equal to the optimal efficiency ((16 data cycles) / (16 data cycles + 1 address cycle)) ~ 94`
14:15
vup
the reader actually submits addresses in parallel to receiving data, so the ddr controller can do a lot of pipelining
14:16
vup
you have to consider, that the zynq side has a large fifo and probably quite sophisticated transaction combining / pipelining / etc logic
14:21
EmilJ
So you're saying that doing a lot of single AXIword transactions right one after each other is nearly equivalent to bursts, when writing to DDR? Reads should behave the same, there's no major fundamental difference right
14:22
vup
EmilJ: I don't think we tested single word transactions for the writer, atleast I cannot recall the results
14:23
EmilJ
then what was being compared to what? I thought you were comparing burst length 1 to burst length >1
14:23
vup
EmilJ: for the writer we were comparing sending the address independent from the data vs first sending the address and then all the data, before sending the next address
14:24
vup
(for writing)
14:26
EmilJ
Ah, okay - so you were delaying WVALID in a burst transaction
14:29
vup
kind of
14:30
vup
https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/7370da1409d3532774fce4797d5e759a075bd7d2/src/lib/bus/axi/buffer_writer.py
14:30
vup
it was just
14:30
vup
1. do a address transaction
14:30
vup
2. send the data burst
14:30
vup
repeta
14:30
vup
*repeat
15:15
BAndiT1983
changed nick to: BAndiT1983|away
15:21
comradekingu
joined the channel
15:35
anuejn
EmilJ: the axi reader currently doesnt do bursts mainly because of lazyness
15:36
anuejn
implementing that would not be too hard (just implement a "burster" core on top of the curent reader)
15:36
anuejn
we didnt do any benchmarking before doning design decisions on the reader
15:36
EmilJ
yeah that's what I was thinking I might do so I actually finally contribute something lol
15:37
anuejn
:)
15:37
EmilJ
so a FIFO with a timeout should get us there right
15:39
EmilJ
by the way I'm confused about how the AXI reader has an output payload (that one ends up being None in the image_stream case right) as well as output out_of_band_signals
15:55
BAndiT1983|away
changed nick to: BAndiT1983
16:51
Bertl
off for now ... bbl
16:51
Bertl
changed nick to: Bertl_oO
19:10
mumptai
joined the channel
22:44
BAndiT1983
changed nick to: BAndiT1983|away
23:16
danieel
left the channel
23:26
danieel
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