Current Server Time: 23:05 (Central Europe)

#apertus IRC Channel Logs

2013/08/25

Timezone: UTC


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se6astian
afternoon gentlemen!
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14:42
Bertl
morning everyone!
14:42
se6astian
hello!
14:43
se6astian
great, news we got another high level developer interested
14:45
Bertl
so who is it and what does (s)he develop?
14:46
se6astian
check your emails :)
14:46
FergusL
awesome news on the mailing list
14:49
se6astian
time too cook :)
14:59
Bertl
good idea ...
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17:06
se6astian
Seems like we finally found someone to properly review the PCB layout
17:06
se6astian
...one day after we ordered ;)
17:22
Bertl
well ... so far common places and hand waving
17:23
Bertl
but yes, input is always appreciated
17:28
dmj_nova1
I've been hearing recommendations for kicad
17:33
Bertl
yeah, I would have preferred kicad, it has become quite useable
17:33
Bertl
but the problem is, it is still lacking a lot of features and it would have taken me a lot longer to get there with kicad
17:34
Bertl
we will probably convert the eagle files to kicad later
17:37
dmj_nova1
yeah, I figure that's a good idea long term
17:40
Bertl
one 'problem' with kicad (might be considered a feature :) is that it separates schematic parts from footprints
17:40
Bertl
another is that foward/backward annotation is quite cumbersome
17:41
Bertl
but as cern has a project running to make kikad a replacement for altium, I'm sure this will improve over time
17:41
Bertl
*kicad even
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jucar2
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17:43
Bertl
se6astian: btw, did you realize that lu_zero payed a visit to the channel?
17:43
Bertl
and showed some interest to help us with the userspace streaming once we are there
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18:01
se6astian
ah, no I didnt notice that
18:01
se6astian
lu_zero, do we have any other info on him as well?
18:02
se6astian
What do you think of Gregs feedback/questions: according to the FMC specification, CLK are inputs only, they cannot
18:02
se6astian
feed the clock. Probably ZYNQ devkit can do this but it may not work
18:02
se6astian
with other FMC carriers.
18:02
se6astian
- in the case of the FPGA, if you want to use hardware serdes, you
18:02
se6astian
must use local clock inputs. Using general CLK that is often routed to
18:02
se6astian
another bank may be wrong idea. Did you try to synthesize the FPGA
18:02
se6astian
core with ioserdes? I would suggest using LA00/01 and LA17/18 as clock
18:02
se6astian
inputs because they should to the local clk inputs. But I didn't
18:02
se6astian
analyze your devkit, we had troubles in the case of fast ADCs with
18:02
se6astian
serial outputs that somebody routed to global clk inputs.
18:20
Bertl
I've replied to the mail :)
18:21
Bertl
https://github.com/lu-zero
18:22
se6astian
perfect!
18:22
se6astian
lu-zero, interesting
18:23
se6astian
userspace-streaming would that be the Ethernet video stream software for example?
18:23
Bertl
yeah, jucar1 introduced him to this project
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Bertl
as he has some experience with ffmpeg, codecs and kernel drivers, I think that might be valuable help
18:24
se6astian
wonderful!
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ApertusWeb0
hello. this is gabe with the zed board. anyone there?
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