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#apertus IRC Channel Logs

2019/07/25

Timezone: UTC

1
03:31
Bertl_oO
apurvanandan[m]: in 10 bit, 1BC starts with a '0' and ends with two '0' so there is little chance that a '1' can sneak in because of bad alignment
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03:31
Nira
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04:11
Bertl_oO
off to bed now ... have a good one everyone!
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04:11
Bertl_oO
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06:08
BAndiT1983|away
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07:47
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08:01
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08:57
Nira|away
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12:27
Nira
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12:44
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13:00
Bertl_zZ
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13:00
Bertl
morning folks!
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13:07
Bertl
apurvanandan[m], aSobhy: how's the status? any progress?
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13:18
apurvanandan[m]
Bertl: I know exactly which module is not working, and now I am trying to find the problem in it. The sampling in DDR at very first step is going wrong, after that whatever data is received is decoded accordingly and sent ie rest of codes does it job fine, only DDR X4 needs to be fixed
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13:18
apurvanandan[m]
Don't know how 1BC can be received as 1BD
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13:19
Bertl
so what is going wrong there?
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13:20
apurvanandan[m]
I have strongly believe there is some delay issue or it is making the delay wrong in between the data transfer
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13:21
apurvanandan[m]
That is the update delay control code
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13:24
Bertl
where is the code for that?
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13:26
apurvanandan[m]
I am making that again, because earlier I trusted IPexpress of Diamond to make that for me
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13:27
apurvanandan[m]
Previous one is here: https://github.com/apurvanandan1997/BER_measurement/blob/master/MachXO2/Receiver/ddrx4_gearing.vhd
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13:29
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13:35
Bertl
don't see any dynamic delay in this code ...
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13:36
Bertl
anyway, it is probably a good idea to write it yourself
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13:37
apurvanandan[m]
No I mean that there is a module ddrx4_rx_sync which takes a uddcntln signal for updating the delay code passed to 90 degree clock shifter on basis of PVT variation
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13:38
apurvanandan[m]
I highly doubt it is useless : https://github.com/apurvanandan1997/BER_measurement/blob/master/MachXO2/Receiver/rx_sync.vhd
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13:40
apurvanandan[m]
Just scroll through that rx_sync.vhd
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13:41
Bertl
well, I'm not sure how you will compensate PVT variation if you cannot adjust the delay?
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13:45
apurvanandan[m]
There is a primitive DQSDLLC that generated required delays using master DLL
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13:45
apurvanandan[m]
https://ibb.co/sQnnkmY
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13:46
apurvanandan[m]
It generates the DQSDEL code sends to the delay module for shifting clock to 90 degree
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13:48
apurvanandan[m]
So it takes uddcntln signal which 'holds/updates control to delay code before adjustment' as written in documentation (not clear exactly)
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13:49
apurvanandan[m]
But earler when only constant data was being received the problem was in this uddcntln signal only, after I changed it the alternating data started being received properly but only ABAB types
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13:49
Bertl
you are aware that those are all elements used for DDR memory access and control
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13:50
apurvanandan[m]
Yes, have somewhat idea
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13:50
Bertl
so they might not always do what you expect with serial transmissions
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13:52
Bertl
you might want to start with x2 or even x1 DDR for testing
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13:56
apurvanandan[m]
What procedure do you suggest as an alternative?
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13:58
Bertl
you have phase adjustment on the PLL and you can add dynamic delay to the data (and clock if needed)
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14:02
RexOrCine|away
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14:03
apurvanandan[m]
But then I will have to find the center of the eye
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14:03
Bertl
as we discussed a long time ago
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14:04
Bertl
i.e. that is what link training is all about
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14:08
apurvanandan[m]
Ok If it doesn't works I will switch to the plain method
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14:31
Bertl
no hurry, it's still a day and 4 hours till the end of the 2nd evaluation :)
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15:00
Nira|away
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15:25
RexOrCine
We're going to disconnect the dark box Beta. It'll be offline for the next three hours. Any problems ping me.
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15:28
Bertl
thanks, should be no problem at all
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15:37
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16:43
aSobhy
I'm about to run on beta within an hour
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16:44
Bertl
note: your Beta should be still available
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16:44
aSobhy
currently generating the bitstream files
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16:44
Bertl
sounds good!
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16:46
aSobhy
is the " dark box Beta" include the Beta_e ?
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16:46
Bertl
nope
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16:46
Bertl
separate unit
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16:47
aSobhy
ok so the beta_e available in the next hours ?!
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16:49
Bertl
yep
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16:49
Bertl
it is available right now :)
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16:51
aSobhy
OK thanks Bertl :)
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16:51
Bertl
you're welcome!
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19:28
BAndiT1983
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19:28
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19:41
Bertl
aSobhy: how is the Beta testing going?
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19:44
Nira
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20:00
intrac
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20:03
RexOrCine
OK the dark box camera is now back online. Thanks for your patience.
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20:10
aSobhy
I get stuck in bits map and apurvanandan[m] helped me
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20:10
aSobhy
I thought it will be easy
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20:14
Bertl
yeah, that's a prominent misconception :)
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20:14
BAndiT1983
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20:15
BAndiT1983|away
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20:48
RexOrCine
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21:18
Nira|away
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21:20
aSobhy
Bertl how I assign an address for a register in lattice
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21:21
Bertl
what do you mean?
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21:21
aSobhy
I want to assign an address to the final register that I accumulate in it the error occurred
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21:22
Bertl
what 'address'?
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21:23
aSobhy
address in the memory
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21:23
Bertl
what 'memory'?
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21:24
Bertl
I can only presume you are talking about some kind of memory mapping the register
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21:25
aSobhy
yes
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21:25
Bertl
but as the MachXO2 is not a SoC, i.e. doesn't have any hardened CPU/MCU there, you would need to add your own CPU/MCU core to 'map' anything
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21:26
Bertl
as I mentioned a few times before, if you want to output debug information from the MachXO2, you need to either do it via the PIC or via dedicated LVDS lines to the Zynq
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21:30
apurvanandan[m]
Bertl: For how many cycles should we do word alignment?
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21:31
apurvanandan[m]
For how long I mean
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21:31
Bertl
I'd say till it is aligned :)
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21:31
Bertl
how long should that take? at most N cycles where N is the number of bits
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21:32
aSobhy
but it is 12 bits width It can't fit to the PIC pins
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21:32
Bertl
so you need to use some kind of serial protocol
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21:33
Bertl
like, as mentioned before, SPI, I2C or UART
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21:40
BAndiT1983
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21:42
aSobhy
sorry I'll check for some information and return again
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21:42
aSobhy
I apologize for miss understanding as I didn't slept well for days :/
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21:45
aSobhy
misunderstanding*
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21:53
Bertl
no problem
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21:54
Bertl
off for now too, bbl
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Bertl
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bertl_oO
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00:43
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