Current Server Time: 05:46 (Central Europe)

#apertus IRC Channel Logs

2014/05/25

Timezone: UTC


00:41
jucar
left the channel
01:38
Bertl
off to bed now ... have a good one everyone!
04:46
se6astian
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04:47
se6astian
good morning
06:49
se6astian
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07:11
danieel
hi
07:24
se6astian
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08:45
danieel
se6astian: do you have example of artefacts between rgb/ycbcr modes? on the cable video the most noticable after strong blur is the 4:2:0 of mpeg4
10:37
se6astian
ok time to leave and go voting :)
10:38
se6astian
see you around
10:38
se6astian
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11:37
jucar
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12:07
Bertl
morning folks!
12:27
jucar
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17:03
se6astian
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17:03
se6astian
good evening
17:09
Bertl
evening se6astian!
18:11
se6astian1
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18:14
se6astian
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18:23
troy_s
Bertl: Do you have a link to the YCbCr code?
18:24
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/ycbcr_*.sh
18:25
Bertl
no change to the FPGA bitstream is required
18:25
troy_s
Bertl: Confusing.
18:27
troy_s
Bertl: Is there a proper broadcast scale in there as well?
18:40
Bertl
not that confusing actually, the HDMI encoder can do RGB and YCbCr
18:41
Bertl
so what we do is we simply map the RGB to YCbCr (ITU BT.709 default)
18:46
Bertl
note that the main purpose was to avoid the RG/GB interpolation the hdmi encoder applies to the data, which results in the red/blue borders around sharp edges or thin vertical lines
18:49
jucar
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19:23
sb0
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20:25
jucar
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20:35
jucar
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21:19
skinkie
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21:20
se6astian1
good night
21:20
skinkie
Bertl: Hi, some mails ago I read you comments on grade -1 and grade -2 memory
21:20
skinkie
what is the difference between those?
21:20
se6astian1
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21:23
Bertl
memory? please refresh mine :)
21:26
skinkie
Bertl: i'll try to find the exact phrase
21:27
skinkie
"So as we basically want to use a BUFG to drive the serializer, we need to limit ourself to DDR clocks below 464 MHz (for -1 grade) and 628 MHz (for -2 grade)  which means, that we are roughly 33% short for 1080p50 (non-standard) and 60% short for full 1080p60."
21:27
skinkie
What would -1 grade and -2 grade mean?
21:28
Bertl
ah, in this case it is the speed grade of the Zynq
21:28
Bertl
i.e. the FPGA, it comes in different speed grades
21:29
Bertl
those capable of higher speeds also cost more
21:30
skinkie
but your statement is that even the higher speed is not fast enough for 1080p60?
21:31
Bertl
I'm looking for the email right now to get the context
21:32
skinkie
[axiom-dev] Direct HDMI output via Zynq TMDS
21:32
skinkie
 Tue, Apr 29, 2014 at 5:31 AM
21:32
Bertl
ah, got it now ... thanks
21:33
Bertl
yes, the problem is, that 'within the guaranteed' timing constraints the zynq chip has (on the Microzed)
21:33
skinkie
and you refer to the fact to 'drive the serializer'
21:33
Bertl
we cannot produce a TMDS signal for those resolutions
21:33
skinkie
it is not about capturing from the cmos/ccd?
21:34
Bertl
correct, this is just for HDMI _without_ encoder
21:34
Bertl
with an HDMI encoder, like the ADV7511, we can reach pixel clocks of 225MHz
21:34
skinkie
but are you also saying that the microzed _is_ capable to get 4k raw out?
21:34
skinkie
(as in: to storage)
21:34
Bertl
which means a TMDS rate of roughly 2.2Gbit per channel
21:35
Bertl
the microzed itself probably not, the AXIOM Beta will be
21:35
Bertl
(capable to get 4k raw out that is :)
21:36
skinkie
after i finish the promised stuff, i deeply want to get into the fpga part as well
21:36
skinkie
but i need some proper references/guidelines
21:37
Bertl
like?
21:38
skinkie
(the fast linux boot / development sdcard boot), fpga resources: where to start how to make useful VHDL for it
21:41
sb0
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21:48
Bertl
I see, well, it's not that hard to get simple VHDL working
21:48
Bertl
we've produced a lot of examples during development
21:52
skinkie
Bertl: is there already some architecture design what parts should be developed?
21:54
Bertl
yes and no, there is a rough design based on the experience with the Alpha
21:55
Bertl
but we should probably spend some time (in the near future) discussing the boot and debug environment
21:58
Bertl
i.e. how to update certain elements, how boot in general is supposed to work, what kind of emergency measure are possible/required and what kind of hooks/interfaces/etc between arm and fpga we want/need
22:07
Bertl
anyway, off for a nap now ... bbl
22:36
jucar
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23:01
troy_s
Bertl: Interesting. So there's some sort of CbCr conversion that the encoder applies by default?
23:14
skinkie
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