Current Server Time: 02:37 (Central Europe)

#apertus IRC Channel Logs

2020/03/25

Timezone: UTC


00:32
Bertl
off to bed now ... have a good one everyone!
00:32
Bertl
changed nick to: Bertl_zZ
00:36
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05:24
BAndiT1983|away
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06:20
Bertl_zZ
changed nick to: Bertl
06:20
Bertl
morning folks!
07:28
preetimenghwani[
Morning bertl!
09:05
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BAndiT1983
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BAndiT1983|away
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11:12
omar31
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11:21
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11:41
se6ast1an
need some swarm help :)
11:42
se6ast1an
can you all measure HDMI connectors you have and see if any of them is thicker than 10-11mm (lower right dimension of https://legitreviews.com/images/reviews/2174/redmereconnectors_550.jpg )
11:45
Bertl
hmm, basically all our HDMI connectors are thicker than that :)
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11:56
BAndiT1983
5mm? just measured general HDMI cable i have here, 11.5mm
11:57
BAndiT1983
could also be 10, but it has grip stripes on top, so the measurement is bigger
11:57
BAndiT1983
hope the cable is stable with 5mm
11:58
BAndiT1983
https://images-na.ssl-images-amazon.com/images/I/61K5eKUk7EL._SX679_.jpg
12:00
BAndiT1983
somehow i can'T believe the 5mm, as the images show much thicker shell and standard hdmi height is 4.5mm -> https://www.amazon.com/Rosewill-RCHN-12002-6-Feet-RedMere-Technology/dp/B00BMEZ04O
12:03
Bertl
all the HDMI connectors we use measure slightly over 14mm
12:06
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12:38
BAndiT1983
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12:38
omar31
Hello Bertl
12:38
omar31
I have a question
12:39
BAndiT1983|away
changed nick to: BAndiT1983
12:39
omar31
you said before that we can do DDR without using any special units by simply sampling at both clock edges
12:41
omar31
I am trying to do that but have the following error when synthesizing:
12:41
omar31
Asynchronous load of non-constant data is not supported
12:43
omar31
I am using Synplify Pro synthesizer on Lattice diamond
12:47
Bertl
what does your code look like?
12:49
omar31
Inside the process I use: if rising_edge(clk) or falling_edge(clk) then ..
13:28
Bertl
pastebin?
13:29
berto_bxl
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13:29
omar31
Oh you meant the whole code?
13:33
omar31
https://pastebin.com/raw/y5LA5E3B
13:34
omar31
The code works fine when using single data rate
13:35
BAndiT1983
are this big indentations normal?
13:37
omar31
Sorry, it needs some formatting as I did not finish it yet
13:37
vup
BAndiT1983: its tabs
13:39
BAndiT1983
vup: so it's how it usually looks?
13:39
BAndiT1983
am not that deep in FPGA topic, tried several times, but as i don't have proper project for it yet, haven't continued
13:39
vup
yes, I think 4 or 8 spaces is the normal size for tabs
13:56
berto_bxl
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13:56
Bertl
omar31: rising_edge() and falling_edge() in the same process cannot be properly synthesized by almost any tools
13:56
Bertl
some tools report an error, others silently ignore one of them
13:57
Bertl
so this is a problem with your code :)
13:59
omar31
Ok, but what did you meant by sampling at both clock edges?
14:00
Bertl
there is no problem with sampling a signal in more than one process
14:01
Bertl
and each process can have its own rising/falling_edge condition
14:02
omar31
I already tried separating the process like that but with the same code inside each one, but had the same error
14:03
Bertl
pastebin?
14:08
se6ast1an
thanks for the hdmi connector measuring
14:09
omar31
Bertl: it actually worked when I tried it right now, I think I missed something the first time, sorry
14:09
RexOrCine
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14:10
Bertl
happens ... make sure to get the formatting right though as it often helps to identify problems early
14:10
omar31
Ok, thank you
14:16
Bertl
no problem
14:32
Bertl
off for now ... bbl
14:32
Bertl
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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