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| 04:24 | Bertl | morning folks!
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| 05:30 | sagnikbasu | Hi Bertl. check this link, its kind of a rough proposal I have made, https://github.com/sagniknitr/GSoC-Apertus/blob/master/Proposal.md
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| 05:33 | Bertl | is there a specific reason for Verilog? (just curious)
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| 05:35 | Bertl | the 'Week 4' tasks do not make much sense, as the filter will not get in direct contact with LVDS anywhere, i.e. the data stream has already been received from the sensor when the filter is applied and the output data will not be sent over LVDS before a lot more processing happens
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| 05:36 | Bertl | nevertheless, we concluded that some 'input module' for stream decimation and maybe even reordering (bayer pattern, etc) would make a lot of sense and similar an 'output module' which then handles and packs the data accordingly
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| 05:38 | Bertl | in 'Week 3' the 'reach minimum latency' doesn't make too much sense to me, here is why:
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| 05:39 | Bertl | for a NxN filter, you need to keep a buffer of at least (N-1) lines to work with, which means that the output of the filter will also have at least N-1 lines worth of delay (latency)
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| 05:40 | Bertl | of course, it makes no sense to buffer more lines than actually required but on the other hand, it doesn't matter if you add the time for another line (extreme case) to the latency
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| 05:41 | Bertl | so, optimization should focus on bandwidth and throughput as well as minimizing the resource usage while maximizing the efficiency
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| 05:41 | usmankhan | Hello Bertl, I was a bit caught up with exams in the past week. I will revise my proposal today
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| 05:42 | Bertl | usmankhan: no problem
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| 05:43 | Bertl | sagnikbasu: I'd also add a block (week or so) for creating a test bench and proper test setups for the filter, to verify functionality and, if applicable, error range
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| 05:48 | Bertl | the links all go to your git account ... you might want to link the specific repository there
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| 05:50 | sagnikbasu | thanks Bertl for the feedback..I will get back with the necessary changes
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| 05:51 | sagnikbasu | This was only a draft proposal..I will definitely change the link address
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| 05:51 | Bertl | no problem, just giving feedback where possible
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| 05:52 | sagnikbasu | and for the question "why verilog?" , just my habit as I have done most of my reconfigurable design labs in verilog..
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| 05:53 | sagnikbasu | also I find verilog HDL concise and clear
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| 05:54 | Bertl | I was just asking because basically all of the AXIOM Beta code is VHDL (partially VHDL-2008)
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| 05:54 | Bertl | welcome Kshitij!
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| 05:54 | Kshitij | Hi Bertl
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| 05:55 | Bertl | sagnikbasu: but I don't see a problem with a mixed design, you just need to make sure that it integrates seamlessly
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| 05:55 | sagnikbasu | of course..that will be my target for this project..
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| 05:56 | sagnikbasu | oh gtg...bye...
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| 05:56 | Bertl | personally I think Verilog is too much like C, so it somewhat tends to mislead you and forget that it is actually an HDL :)
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| 05:56 | Bertl | no problem, cya
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| 07:09 | usmankhan | Bertl, can you check the schematic here? https://github.com/usmanwardag/gsoc17_proposal/blob/master/Buck.pdf
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| 07:10 | usmankhan | The idea is that as the feedback voltage (Vf) increases, the output of the negative feedback amplifier decreases
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| 07:11 | usmankhan | Accordingly, we can design a pid controller to adjust the duty cycle
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| 07:14 | usmankhan | Oops, it seems like I have positive feedback op-amp in the schematic, but anyway the op-amp can be either and we can design logic accordingly
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| 07:21 | Bertl | looks good so far
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| 07:22 | Bertl | what tools did you use to create the schematic?
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| 07:22 | usmankhan | Ok great
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| 07:23 | usmankhan | draw.io
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| 07:25 | usmankhan | I'll be right back
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| 07:26 | Bertl | you probably need to extend the 'Feedback' block to cover the positive input as well, because that's probably the only way to add some kind of hysteresis
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| 07:50 | usmankhan | Ok, I'll do that
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| 07:53 | usmankhan | What hysteresis range would you recommend?
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| 07:58 | Bertl | it should match the ripple voltage I guess (probably be somewhat lower)
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| 08:01 | usmankhan | Ok
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| 09:04 | Bertl | off for now ... bbl
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| 16:38 | Elbehery | I would really appreciate your feedback about my current draft proposal [https://github.com/ELBe7ery/i2c_draft_gsoc/blob/master/Proposal/AbdelrahmanElbehery.md]
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| 17:26 | RexOrCine[m] | Elbehery - Thorough. Looks good.
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| 17:28 | Elbehery | Thats great :), any comments or things you suggest i should edit at the moment ?
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| 17:29 | Elbehery | I really appreciate taking the time to look at this thanks so much :)
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| 17:33 | RexO | Well I don't get too involved with technical stuff. There are a handful of spelling errors or words missing, which is ok, but it was good to see that you'd made the effort to answer all the questions fully. Good to meet you.
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| 17:35 | Elbehery | Great, i will check all the grammar mistakes and correct them, thanks so much
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| 18:45 | RexO | I've got four applications / proposal links listed thus far: Elbehery / Mehrikhan / Usmanwardag / Sagnik Basu .... If you've linked us and I've missed it please let me know.
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| 18:47 | RexO | ... or email on team @ apertus . org
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| 19:11 | anuditverma | Hi RexO, I will be submitting in a while
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| 19:12 | anuditverma | almost finished with my draft
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| 19:12 | RexOrCine[m] | Understood. No rush or anything, but I'm logging applications centrally.
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| 21:53 | Bertl_oO | Elbehery: looks really good, I would add a small, final point which addresses future improvements and developments in this area, like for example changes to the pwm circuitry or similar
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| 21:56 | Bertl_oO | regarding oversampling for the I2C slave: I think that is not required at all, but a good point and actually depends on T731 in our case ... note that the clock domain crossing between I2C slave and PWM unit needs to be addressed in any case
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| 21:58 | Bertl_oO | small detail though: the FPGA part of the FAN controller will not be on a Xilinx FPGA, as the circuitry is connected to the Lattice MachXO2 routing fabric, so you need to integrate it there (you can still test and simulate it on Vivado if that is something you prefer, for whatever reason)
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| 22:02 | Bertl_oO | side note: simulation via iverilog (Icarus Verilog) might be in the FOSS/OH spirit of the project and together with GTKWAVE it should provide all you need for both, functional as well as gate level simulation
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| 22:49 | Elbehery__ | Thanks soo much for taking the time and viewing my proposal really appreciate this
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| 22:50 | Elbehery__ | Regarding the improvement section. Do you think this should be considered in the schedule ?
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| 22:50 | Elbehery__ | Regarding the 2nd point i totally agree
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| 22:53 | Elbehery__ | Regarding the 3rd point. was reading earlier char logs and i have totally missed this, you mentioned earlier this is going to be implemented on the Lattice FPGA, i will edit this since no point of working on xilinx tool. Also Lattice tool comes with the reveal tool which is really good for the debugging stage
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| 22:55 | Elbehery__ | Regarding yosys and iVerlog thats great, i am familiar with both of them, i have even written some tools for faster simulations and compiling via atom text editor so this is good for me i will be using them
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| 22:55 | Elbehery__ | chat logs *
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| 22:56 | Elbehery__ | Any comments on the suggested schedule ?
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