#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

good morning

hi all

se6astian:

hey intracube! how's going?

are you here Bertl ?

somewhat busy, but around

makes sense

for exemple

i would like to create a "block" (IP) which can take a 32 bits signal in input (= the random number) and has 4 (data) + 1 (clock) serial output (which could be connected to lvds pins)

i don't speak about the coding now, just take a 32 bit signa and send it to severals ldvs pairs

i need :

1*

check out the *pll*.vhd files in the cmv_io2

the PLL/MMC are hardened peripherials inside the FPGA

you can instantiate them like a black box and the tools will fill in the functionality

so it is a inputclock

ok

- 1 input "Data Enable" which indicate that there is a data on the 32 bits signal and that I can send it on the lvds lines

correct ?

you usually want to send data back to back, so you will enable for multiple of 32 clock cycles

so that "one" clock cycle is for a 32bit word

at the bit clock, yes, usually you will use the work clock or at least a byte clock to simplify timing

the byte clock will also be the clock used for the serializer input data

one at the "word" rate of the serializer (for 10bit codes, that is 100MHz)

if you serve 4 outputs, it would also be 100MHz

are they from PL ?

yes, usually you have an external clock, let's say 100MHz and you generate all the required frequencies/clocks via PLL/MMC

so the "data enable " signal should be synchronized on the 25Hz clock

that means that the IP send the 32 bits number at each period of the 25MHz

yep, that would make sense in this case

BAndiT1983 created T340: Check communication between MediaExplorer and context. http://lab.apertus.org/T340

off for a nap ... bbl