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#apertus IRC Channel Logs

2016/01/25

Timezone: UTC


01:01
arpu
left the channel
01:39
John_K
I've been using backblaze's normal backup product for 3 years and am very happy with it
01:39
John_K
client side encryption with a key I specify
01:39
John_K
I've also built one of their storage pods too, I like that they open-sourced their design
03:06
davidak
left the channel
03:42
aombk
hmm, i will need 60 days to upload my data
05:00
John_K
eep, can you mail any of them a hard disk to seed the backup?
05:56
davidak
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06:21
aombk
John_K, i tried their service, i dont like the backup everything approach, i want to choose what to backup
06:58
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07:23
jucar
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07:33
tezburma
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07:34
davidak
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07:43
John_K
then I'd probably look at tarsnap, those are the only two i'd trust with my data
08:40
se6astian|away
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08:41
se6astian
good morning
08:41
Bertl_oO
morning se6astian!
08:41
Bertl_oO
changed nick to: Bertl
08:54
AXIOM-HQ
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09:32
niemand
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09:32
John_K
good morning
09:33
John_K
so when I'm ready to talk to the sensor, should I run cmv_snap3 ?
09:34
Bertl
no, you should first load the bitstream and then try cmv_init.sh
09:34
Bertl
that should return with a single register value, which is the sensor temperature
09:36
John_K
so cmv_hdmi3.bit?
09:36
Bertl
yep, send it to /dev/xdevcfg
09:37
John_K
ok, I'm just trying to check that the voltage pins of the socket on the sensor board have the appropriate voltages first
09:37
Bertl
yes, please do so :)
09:38
Bertl
also, you can use the pincheck to verify most of the sensor data lines as well
09:38
Bertl
i.e. activate the check_pin20.bit in the FPGA
09:38
John_K
so buzz out everything?
09:39
Bertl
then run ./check_pin20
09:39
John_K
with or without a CMV?
09:39
Bertl
it will show you all shorts/connections between lines
09:39
John_K
without I'm guessing
09:39
Bertl
without the sensor, but with the socket
09:39
Bertl
i.e. SFE but no sensor
09:40
John_K
pull-up JX1_LVDS_2_P
09:40
John_K
pull-up JX2_SE_0
09:40
John_K
pull-up JX2_SE_1
09:40
John_K
connect JX1_LVDS_22_N <-> JX1_LVDS_22_P
09:40
Bertl
that doesn't look too bad :)
09:40
Bertl
the JX1_LVDS_2_P comes from the MicroZed
09:40
John_K
are any of those problems?
09:40
Bertl
the LVDS_22 comes from the termination resistor on the clock line
09:41
Bertl
now try to bridge an LVDS pair on the socket
09:41
Bertl
and it should show up as connect
09:41
John_K
hrm, let me see what I have to do that with
09:41
Bertl
you can also pull each individual line down to GND for test, but use a 200R resistor
09:42
Bertl
there is another way you can test the connections if you prefer to use a scope/analyzer
09:43
Bertl
in this case you use the tag_pin20.bit bitstream
09:43
John_K
which row is unused in the socket again? the bottom one that's short two pins?
09:43
Bertl
and then each IO will broadcast its ID as serial bitstream :)
09:46
John_K
oh neat
09:47
Bertl
the sensor is placed in the upper left corner of the zif socket
09:49
John_K
hrm, I'm trying to short them in the socket with a 30GA wire, but am seeing nothing new on check_pin20
09:49
John_K
N05_P/N
09:49
John_K
pings 7 and 8 from left on top row
09:49
John_K
pins*
09:49
Bertl
try a different one or try a single one to GND (via 200R)
09:50
Bertl
while the pair test is nice, it has twice the chance to fail if a connection is bad
09:50
John_K
don't have an easy way to do it to GND via a resistor
09:50
Bertl
also note that the pins on the ZIF are not easy to probe
09:50
Bertl
i.e. you want to put two tiny cables in the socket and then lock it
09:51
Bertl
a simpler way for testing is to use a uPGA socket or socket strip
09:51
Bertl
and put that into the ZIF socket
09:53
John_K
ok got it to work
09:53
John_K
N_01_P/N aka JX1_LVDS_13_N/P
09:55
John_K
hrm, I think the top left pin should be GND but I'm reading 3v0
10:00
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/Sensor_Check.pdf
10:02
John_K
so H1 (GND) should be the top-left most hole in the socket right?
10:03
Bertl
yes, that's what the diagram shows (blue is GND)
10:03
John_K
ok. I measure 3v0 there
10:04
Bertl
well, that's not really good :/
10:04
John_K
maybe one of my board orientations is wrong?
10:04
Bertl
maybe, but they are all labeled/marked
10:05
John_K
they aren't on my rev :\
10:05
Bertl
really? strange
10:05
Bertl
okay, so the main board only attaches one way
10:05
Bertl
i.e. that is keyed, same goes for the power board
10:05
John_K
do all of the board version blocks orient the same way?
10:06
Bertl
so we can assume, you have those right
10:06
John_K
I'm worried about dummy interface and sensor
10:06
Bertl
the dummy interface has arrows on it which point upwards
10:06
Bertl
and yes, the labels/text on all boards are the same orientation
10:07
John_K
hrm
10:07
John_K
and the sensor board lock bar is at the "top" as well?
10:07
Bertl
yep
10:07
John_K
puzzling
10:07
Bertl
also there shouldn't be a problem, as both the sensor and dummy interfaces are rotation symmectric
10:08
John_K
they are?
10:08
Bertl
so while you won't get the correct connections, it shouldn't put GND on a power rail
10:08
John_K
ah
10:08
Bertl
the design is such, that the sensor can be rotated 180 degree without problems
10:09
Bertl
and with a full interface board, that would even work and be detectable
10:09
John_K
oh wait, it was probing as 3v0 with the lock closed
10:09
John_K
with the lock open it's 1ohm short to GND
10:10
John_K
I was probing with a tiny DMM probe that fits in the holes
10:11
Bertl
well, there is S_VS right below that one
10:11
John_K
yeah that looks to be what happened
10:11
John_K
ok so probe with the socket open
10:12
Bertl
as I said, I usually stick in a uBGA socket (strip) and lock it in place to probe
10:12
Bertl
unless I'm probing a single location
10:12
John_K
i don't have such a small size available here
10:12
John_K
luckily my DMM probes fit
10:13
Bertl
okay then, just make sure that there is no short circuit when you close the zif socket
10:13
Bertl
because if that happens with the sensor plugged in, you might grill it
10:17
John_K
well it it shorted 3v0 to GND we'd know I think
10:17
John_K
btw is 2.5v ok for VIO?
10:20
John_K
it LVDS pairs are at 2.5v, but the chip says mav 2.4v
10:20
John_K
was just curious what you're driving it at
10:26
Bertl
for the test the zynq uses CMOS25 config
10:26
Bertl
when operating in the intended way, those are configured as LVDS25
10:26
Bertl
which will have the expected swing
10:26
John_K
ok
10:27
John_K
I've verified the voltages, I guess I might give the sensor a try
10:27
Bertl
good :)
10:27
John_K
be back in 5
10:50
John_K
hrm
10:51
John_K
cmv_init.sh prints out 0
10:51
John_K
./power_init.sh
10:51
John_K
./power_on.sh
10:51
John_K
cat cmv_hdmi3.bit > /dev/xdevcfg
10:51
John_K
/cmv_init.sh
10:51
John_K
0x00000000
10:51
Bertl
that means that the SPI communication with the sensor is not working properly
10:52
John_K
sensor pin 1 locator dot should point at the lower left of the socket correct?
10:52
Bertl
check the light pink pins on the top-right corner
10:52
John_K
oh wait, do I need PIC or CPLDs programmed for that?
10:53
Bertl
yep, index pin A1 is on the bottom left
10:53
Bertl
ah, yes, you need the RFE for this to work
10:53
John_K
aha
10:54
Bertl
I usually test all the functionality board by board
10:55
Bertl
so once I get to the sensor board the PIC and FPGAs are already working
10:55
John_K
well that's why I'm keeping track of this so I can throw it on the wiki
10:56
John_K
it's always fun being the 2nd person to bring up a system
10:56
John_K
so nothing in that directory is jumping out at me as RFE bitstream or a way to program it
11:01
Bertl
let's see what scripts/code you have (sec) I don't think we have the latest tools for that on the image
11:02
John_K
sure, I see some icsp and pic related stuff
11:03
Bertl
remove the SFE (just to make sure)
11:03
Bertl
(or at least the sensor)
11:04
Bertl
then activate the icsp.bit (md5: f671a9a98f7bbbc38636aab43954e979)
11:04
John_K
sensor is warm to the touch
11:04
John_K
booting back up now
11:05
Bertl
that is kind of expected, it usually gets about 10°C over room temperature when not cooled
11:05
John_K
feels about right
11:06
John_K
my icsp.bit is different
11:06
John_K
# openssl md5 icsp.bit MD5(icsp.bit)= 86005abfb43edbc4383e8450968c5d2b
11:06
Bertl
okay, do you have a script called icsp_sel?
11:06
John_K
no
11:06
John_K
i have 4 python files
11:07
John_K
icsp.py, dump, prog, off
11:09
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/icsp.bit
11:09
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/icsp_sel.py
11:09
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/icsp.py
11:11
Bertl
give me a few minutes to get the hardware you have together here
11:12
John_K
no worries, I'm glad for the help
11:15
Bertl
do you have the 3xPMOD assembled as well?
11:17
John_K
I do not
11:19
Bertl
okay, it would be helpfull to get at least the LEDs soldered on
11:19
Bertl
LEDs and resistor networks that is
11:19
niemand
left the channel
11:19
Bertl
simplifies testing of the FPGA
11:20
Bertl
anyway, my setup should now be similar to yours
11:21
John_K
ok
11:21
Bertl
when you load the icsp.bit the blue led on the microzed goes on
11:21
John_K
i'll give that a shot now
11:21
Bertl
./icsp_sel.py A
11:21
Bertl
should slect the west side FPGA
11:21
Bertl
(or at least the bus to the PIC)
11:22
Bertl
next step: i2cdetect -r -y -a 2
11:23
John_K
got he blue light
11:23
John_K
the*
11:24
John_K
I get all --'s except for 70: 70 in colum 0
11:24
Bertl
that's fine
11:24
Bertl
now run ./icsp_picid.py
11:24
John_K
I don't have that script
11:25
Bertl
okay, sec
11:26
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/icsp_picid.py
11:26
John_K
anything else I'll need? I have to shutdown and swap the sdcard to put new files on right now
11:26
Bertl
why's that?
11:27
John_K
I don't have ethernet nearby here
11:27
Bertl
no laptop nearby?
11:27
John_K
laptop yes
11:27
John_K
I could find a usb stick I guess
11:27
John_K
1 sec
11:28
Bertl
does your laptop have an ethernet jack? is it already used?
11:28
John_K
macbook, no ethernet
11:29
Bertl
thunderbolt?
11:29
John_K
yeah
11:29
Bertl
there is an ethernet adapter for that, IIRC :)
11:29
John_K
there is, I just don't have one here
11:29
John_K
that link is broken
11:30
John_K
aha a folder
11:30
Bertl
yeah, I moved it in one place
11:36
John_K
# python icsp_picid.py
11:36
John_K
b'Z'
11:36
John_K
b'L'
11:36
John_K
b'#3DAF3DAF'
11:36
John_K
b'^'
11:36
John_K
then hangs and the dies with a ValueError
11:37
Bertl
well, that's not good
11:37
John_K
https://gist.github.com/John-K/9c1d9768d34902ebe453
11:38
John_K
i2cdetect showing nothing now
11:38
John_K
selecting it again makes it come back up
11:39
Bertl
yeah, that is kind of expected
11:39
John_K
same behavior with icsp_sel.py B
11:40
Bertl
do you have a gpio.py script?
11:41
John_K
a bunch of scripts that start with gpio_ but not gpio.py
11:41
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/ICSP/gpio.py
11:46
John_K
ok now what
11:47
Bertl
run it :)
11:49
John_K
https://gist.github.com/John-K/d8ae9a045a70cd3b32b8
11:50
Bertl
okay, that looks fine, let's update your kernel and devicetree, maybe the image still has the broken serial driver
11:51
John_K
# uname -a
11:51
John_K
Linux beta 4.0.0-xilinx-00054-g3a450582-dirty #3 SMP PREEMPT Sun Oct 25 07:08:41 UTC 2015 armv7l GNU/Linux
11:51
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/ICSP/{devicetree.{dtb,dts},zImage}
11:51
John_K
Linux version 4.0.0-xilinx-00054-g3a450582-dirty (root@beta) (gcc version 5.2.0 (GCC) ) #3 SMP PREEMPT Sun Oct 25 07:08:41 UTC 2015
11:51
John_K
ok
11:52
Bertl
simply copy it to /boot
11:52
Bertl
run sync
11:52
Bertl
and reboot the Beta
11:54
John_K
ok what to try now?
11:55
John_K
icsp again?
11:56
John_K
aha
11:56
John_K
much better
11:57
John_K
https://gist.github.com/John-K/9c1d9768d34902ebe453
12:01
John_K
similar but different result for B
12:03
John_K
looks like I need a hex file?
12:09
Bertl
better but still not perfect
12:10
Bertl
the ['0x3fff', '0x3fff'] show the vendor/device ID from the pic
12:10
Bertl
which should be ['0x2000', '0x305b']
12:10
John_K
ah
12:11
Bertl
so, for whatever reason, you PIC is not responding
12:11
John_K
ok
12:11
Bertl
power enable and power good was fine on the gpio.py reading
12:12
Bertl
the reset line should switch depending on your sel
12:12
John_K
which one where you looking at?
12:12
Bertl
i.e. either A_#RST or B_#RST
12:12
John_K
they are both 1 right now
12:13
John_K
O1+1
12:13
Bertl
they will get reset during the picid
12:14
John_K
ah
12:14
Bertl
try to specify A and B to the icsp_picid.py
12:15
John_K
values are now the same for both A & B
12:16
Bertl
and do they show the correct PIC ids?
12:16
John_K
picid A and picid B give same value no matter which was selected
12:16
John_K
no
12:16
John_K
still 3fff
12:16
Bertl
means the pic is not properly responding
12:17
Bertl
do you have a scan/image from the main board?
12:18
John_K
onse sec
12:20
John_K
https://kelley.ca/temp/Main_Board_v0.33_r1.1-Top.jpg
12:20
John_K
https://kelley.ca/temp/Main_Board_v0.33_r1.1-Bottom.jpg
12:21
John_K
trying my other main board now
12:23
John_K
still bad IDs on this one
12:24
Bertl
the only difference I can see between my board and yours is R7 (which is not populated on mine)
12:24
Bertl
but that shouldn't be a problem IMHO
12:25
John_K
R7 and R8?
12:25
Bertl
yep
12:25
Bertl
but let's check connectivity for the bus first, I would suspect that something is wrong there
12:26
Bertl
can you attach a proble to *_SCL and *_SDA ?
12:26
John_K
I have a DMM here, I can put a scope on it tomorrow
12:27
Bertl
well, DMM is tricky to see, pulses are short with the default I2C
12:27
John_K
you want me to check for PU's or something else
12:27
Bertl
but we can do a test, sec
12:43
Bertl
nah, unfortunately that is rather complicated to access
12:44
Bertl
what you could do is to write a small VHDL code for the zynq to toggle the SDA/SCL at a known low frequency (<1Hz) which you can measure with the DMM
12:45
Bertl
otherwise your best bet is a scope or logic analyzer
12:46
John_K
yeah I can hook up a logic analyzer tomorrow
12:47
John_K
I should see commands when doing picid?
12:47
John_K
sorry, I've never used PICs before, strictly ARM and MIPS
12:48
Bertl
yeah, the ICSP = In Circuit Serial Programming
12:48
Bertl
will show a number of sequences via clock and dat
12:49
John_K
if there are any other test procedures or instructions on how to program the CPLDs that I can try in 8-12 hours that would be great
12:49
John_K
is ICSP I2C based?
12:49
Bertl
no, but reasonably similar
12:49
John_K
ah ok
12:49
Bertl
well, strictly speaking you don't need the PICs
12:49
Bertl
you can hook up the JTAG port of the RFE lattice
12:50
John_K
oh
12:50
Bertl
and program it directly
12:50
Bertl
the PICs are for handling the FPGAs
12:50
John_K
ah
12:50
John_K
mostly just for programming them or other things?
12:51
Bertl
but the unprogrammed PIC should result in sane defaults for the other FPGA pins
12:51
Bertl
bascially programming and interface/control for the FPGA
12:51
John_K
ok
12:51
John_K
BTW, where can I find FW for the PICs and FPGA?
12:52
Bertl
the PIC firmware (and source) is on your beta image
12:52
John_K
ok
12:52
Bertl
in /opt/PIC/PIC16/PIC16F1718
12:53
Bertl
and can be compiled on the Beta
12:53
John_K
oh, nice
12:53
Bertl
the RFE code is here http://vserver.13thfloor.at/Stuff/AXIOM/BETA/LATTICE/
12:54
John_K
ok cool
12:54
John_K
I'll see what I can get working after I wake up
12:55
John_K
5am here, going to grab 4 hours of sleep
12:55
Bertl
okay, have a good night then!
12:55
John_K
thanks! and thanks again for the help debugging
12:57
Bertl
you're welcome!
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gotta go
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se6astian|away
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21:20
Bertl
off to bed now ... have a good one everyone!
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Bertl
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