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15:38 | Bertl | morning folks!
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15:40 | jhlink | Good morning! :D
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15:42 | jhlink | Hey @Bertl, I'm new to the project, but I'm an embedded developer though experienced in non-RTOS, interrupt-less, single-purpose applications. Basically, embedded software in home appliances!
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15:42 | jhlink | I'd like to being supporting the project, but I was wondering what areas most need tender, love, and care with respect to the current development sprint?
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15:42 | jhlink | Or specifically, what repos.
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15:43 | Bertl | sounds great! so you are mostly on the software side for embedded systems or some hardware hacking as well?
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15:44 | RexOrCine | Welcome jhlink. Thanks for coming!
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15:44 | jhlink | Both! Though if we're getting into specifics, enough hardware hacking to use an oscilliscope, but not enough experience for working out timings.
| 15:45 | Bertl | .o( hmm ... felt like he/she was already there :)
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15:45 | jhlink | Thanks /RexOrCine !!
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15:46 | RexOrCine | How did you find out about the project?
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15:46 | Bertl | okay, so you know your way around a scope and logic analyzer but you prefer to work on the software side, yes?
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15:47 | jhlink | Honestly, probing around the Google Summer of Code site. I've been looking around for open source hardware projects to contribute towards, but I didn't know where to look beyond filter through Github repos by popularity.
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15:47 | jhlink | Also, how do you tag users in IRC? I can't seem to get that right.
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15:48 | Bertl | tag?
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15:48 | jhlink | I'd like to do both, but seeing as I don't have a lot of supporting electronics equipment beyond an oscilloscope, I think software is what I'm limited to.
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15:48 | jhlink | Sorry, oscilloscope, logic analyzer, function gen., etc.
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15:48 | jhlink | Err. User
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15:48 | jhlink | Like, Hey "Bertl"
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15:49 | jhlink | Or how RexOrCine tagged my user name?
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15:49 | jhlink | I may not be using the correct terminology. I'm used to using @ in Slack.
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15:49 | Bertl | ah, well, that is client specific and the magic word there is 'highlighting'
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15:49 | jhlink | hahaha, duly noted.
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15:50 | RexOrCine | I actually typed it... but I suspect it depends on what client you're using. By the way if you're using the IRC window on apertus.org it would be beneficial to source a client.
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15:50 | Bertl | but most clients support auto highlighting for the nick of the client owner
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15:50 | Bertl | i.e. when you (or even I) write 'Bertl', it will highlight
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15:51 | jhlink | Already there, Rex. :) I'm using LimeChat.
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15:51 | Bertl | actually I lied, my client seems to be smart enough not to highlight my own messages :)
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15:51 | RexOrCine | I use Pidgin and it doesn't.
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15:51 | Bertl | RexOrCine: you want the IRC plugin for that on Pidgin
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15:52 | Bertl | nevertheless you can use some attribute characters for most clients like _this_ for *example*
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15:52 | Bertl | which usually is interpreted correctly by most clients
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15:53 | jhlink | Absolutely. Something similar to Markdown, right?
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15:53 | jhlink | It's a wonderfully simple way of messaging.
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15:53 | Bertl | yeah, kind of the great, grand parent of markdown ;-)
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15:53 | jhlink | xD
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15:53 | jhlink | So, Axiom!! What's the dealio?
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15:54 | Bertl | well, tons of places you can work on, but it is a little tricky without having at least parts of the hardware availabl
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15:54 | Bertl | *available
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15:54 | Bertl | what architectures did you work with yet (hardware wise)?
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15:56 | Bertl | i.e. for what kind of CPU/MPU did you write software for
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15:56 | RexOrCine | (... all the deeper reading on various topics is archived on the Wiki - https://wiki.apertus.org/index.php/Main_Page )
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15:56 | jhlink | Nothing in particular. It's mostly been Arduinos and Raspberri Pis. I've got some STM32 boards, but haven't got into for lack of a project.
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15:57 | Bertl | Microchip MCUs like the PIC series as well?
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15:58 | jhlink | Nope! My past job focused more on taking on the shelf devices and delivering products.
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15:58 | jhlink | That said, I'm completely open to learning them.
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15:58 | jhlink | I've got a general understanding of computer architecture, so I'm sure I could pick it up.
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15:59 | Bertl | sounds good, well, we have a bunch of FPGAs (not sure you want to dabble into that yet :) and otherwise mostly PIC16 and PIC32 parts
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15:59 | Bertl | the SoC variety of FPGA (we use a Xilinx ZYNQ) has two hardened arm cores (similar to RPi) so that might be an option too
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16:00 | RexOrCine | Remote access for a camera is available - https://wiki.apertus.org/index.php/AXIOM_Beta_Remote_Access
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16:00 | jhlink | Hahaha, someday soon, I'll hope to buy an FPGA!
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16:00 | jhlink | Yeah! That remote access link was amazing.
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16:00 | jhlink | Part of the reason why I wanted to join this project.
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16:00 | RexOrCine | Brilliant.
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16:01 | Bertl | jhlink: actually they are quite cheap nowadays ... so the entry price level is not a problem anymore
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16:01 | RexOrCine | jhlink: Where are you based?
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16:01 | jhlink | Wait. Price for the FPGAs that Axiom is using?
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16:01 | jhlink | Kentucky, USA
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16:02 | jhlink | While we're on the topic of architecture, one of the questions I had while lurking around the site previously was how all the software pieces were connected.
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16:02 | Bertl | boards featuring a Xilinx ZYNQ can be bought for less than 100 bucks nowadays
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16:02 | jhlink | Maybe it's my inexperience with FPGA that's preventing me from making the mental connections, but I'm not sure how everything is communicating.
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16:02 | Bertl | the development board we use for the AXIOM Beta is around 200 bucks
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16:02 | jhlink | Awesome.
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16:03 | Bertl | so, how does it all connect? ... loosely :)
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16:04 | Bertl | you might want to check the wiki for a general idea how the AXIOM Beta stack is designed
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16:05 | Bertl | https://wiki.apertus.org/index.php/AXIOM_Beta/Manual
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16:05 | Bertl | on the software side, the image pipeline is done in the FPGA
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16:05 | RexOrCine | Specifically 11.2.1.
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16:06 | RexOrCine | (section of the linked manual)
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16:06 | RexOrCine | Sorry, 11.1
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16:07 | Bertl | the various control registers are realized as memory mapped regions
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16:07 | jhlink | Cool, cool.
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16:07 | Bertl | and the arm cores basically do all the orchestration required to make it work
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16:08 | jhlink | Where does the axiom-control-daemon exist in the stack?
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16:08 | Bertl | that is work in progress done by BAndiT1983 when he has some spare time
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16:08 | Bertl | for now, basically all the control and adjustments happen with bash or python scripts
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16:09 | Bertl | which has some issues when you do uncoordinated changes
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16:09 | jhlink | Cool. So, in terms of development, the axiom-beta-firmware is the main repo for development?
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16:09 | jhlink | Bertl: lol. uncoordinated changes???
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16:09 | Bertl | so the 'control deamon' is supposed to step in and address this
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16:10 | Bertl | i.e. make sure that requests and changes are properly serialized
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16:11 | Bertl | handle the various bus interfaces and register accesses and present an easy to use interface to 'the outside'
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16:12 | Bertl | for the current firmware, you want to talk with anuejn and vup as well as se6ast1an_ ...
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16:14 | jhlink | Okay. If I'm understanding this correctly, the Xilinx FPGA is the main board that communicates with all the device peripherals and manages the appropriate device settings.
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16:14 | jhlink | Where's the PIC16 and PIC32?
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16:15 | jhlink | Or I guess, what are their roles in the camera hardware stack?
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16:15 | Bertl | the ZYNQ is on the MicroZed, the development board we use for the AXIOM Beta
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16:15 | se6ast1an_ | I am in the bus on the way home currently so don't expect me to participate much currently
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16:15 | Bertl | the PICs are on the MainBoard and the PowerBoard
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16:15 | Bertl | (and also on the AXIOM Remote)
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16:16 | Bertl | they basically do hardware and bus management as well as help with debugging and bringup
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16:16 | Bertl | (on the Remote, the PIC32 is the main processor)
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16:17 | RexOrCine | jhlink: Would it be possible to get an email address for you please? I've DM'd you.
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16:17 | BAndiT1983|away | changed nick to: BAndiT1983
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16:17 | jhlink | Absolutley.
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16:21 | jhlink | Alright, so. I can understand what the pic may be doing on the PowerBoard, but on the MainBoard is it all of the above? HW, bus management, debug interfaces.
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16:21 | jhlink | I'm looking at the AES-Z7MB-7Z010-G block diagram, and I can't seem to find where the PIC is blocked.
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16:21 | jhlink | On this link. https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-z7mb-7z010-g-3074457345635221604/
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16:22 | jhlink | (I'm setting aside the AXIOM Remote stuff for now. :) )
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16:23 | jhlink | Oh wait. Please ignore those last few messages. I just found the PCB files for the Beta stack.
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16:23 | BAndiT1983 | jhlink, which PIC do you mean?
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16:24 | jhlink | I was looking at the AES-Z7MB-7Z010-G evaluation board, and not the Axiom camera PCBs, sooooo.... I'd like to retroactively pull those weird questions. xD
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16:25 | RexOrCine | jhlink: Well done. I'm in the process of reorganising things so files are easier to find... which Bertl will be pleased to hear.
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16:26 | jhlink | RexOrCine: Please!! xd Frankly, it's a bit of a treasure hunt to find information!
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16:26 | jhlink | xD*
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16:26 | RexOrCine | It's easier said than done of course. Because it's a deep place. But things do improve gradually.
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16:28 | jhlink | Incremental progress is the best strategy for monolithic projects. ;)
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16:29 | jhlink | What PCB software was used to design the boards?
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16:29 | Bertl | Eagle
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16:29 | jhlink | Coool.
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16:30 | jhlink | Out of curiosity, are the board designs version controlled in Github?
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16:30 | jhlink | or wherever, xD
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16:31 | Bertl | whatever yes :)
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16:31 | Bertl | boards have a version and a revision
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16:32 | Bertl | the version changes when something functional or placement specific has changed
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16:32 | Bertl | the revision is upped when we move labels around or do other changes like covering or uncovering vias, adding test points, etc
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16:33 | jhlink | Very cool. Are they centrally managed in a repository?
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16:34 | Bertl | http://files.apertus.org/HARDWARE/AXIOM/BETA/
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16:34 | Bertl | probably not 100% up-to-date, but if you are missing something, just let me know
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16:38 | jhlink | For sure! Thanks Bertl!
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17:07 | jhlink | Okay. I have an idea of how everything is connected now. You've got two pic16 and a couple of MachXO2 FPUs on the main board while stacking it with the Zylinx development board.
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17:07 | jhlink | I didn't realize the dev board was being used for this.
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17:07 | jhlink | Now that I've signed off more or less on that rabbit hole... xD
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17:25 | jhlink | I think it'd be an understatement to say that Axiom is predominately an FPGA/embedded linux project, right?
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17:25 | RexOrCine | Definitely embedded Linux.
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17:26 | jhlink | Rockin'.
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17:26 | jhlink | How are builds currently created?
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17:26 | RexOrCine | Note: I don't program.
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17:26 | jhlink | I noticed there was a task for something like this in the Project board.
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17:26 | jhlink | Hahaha, noted.
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17:27 | RexOrCine | So that question takes me a bit our of my area.
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17:27 | RexOrCine | out*
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17:27 | RexOrCine | (I don't type properly either)
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17:28 | jhlink | No worries.
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17:29 | jhlink | So, given that I don't have a dev. board, I think I'd like to try my hand at the build system.
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17:29 | jhlink | Are there any continuous integration servers that are being run?
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17:29 | jhlink | or used*
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17:30 | RexOrCine | I think so. That's one for Bertl really.
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17:30 | jhlink | Got it. I'll leave questions here and check back later.
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17:31 | jhlink | What's the last known working build that works with qemu? The github release page doesn't list a "Stable" build, hahaha
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17:32 | jhlink | Per T738, could I just pick a stable (LTS) OS that works and roll with it?
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17:33 | jhlink | I think those are all the questions I have for now.
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17:33 | jhlink | I'll check back later for updates. :)
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17:36 | Bertl | check with anuejn and vup for building the firmware
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17:37 | Bertl | should be fairly automated by now
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17:37 | Bertl | for the QEMU part, check with alexML, he has done some work there IIRC
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18:04 | vup | jhlink: yeah no stable releases yet :)
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18:04 | vup | Best to clone the git repo and follow the readme
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18:05 | vup | https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/makefiles/README.md
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18:06 | vup | ./makefiles/docker-make.sh qemu-shell should get you started
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18:06 | RexOrCine | Bertl: Have you any Triple PMODs that can be photographed?
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18:26 | Bertl | will check
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20:58 | RexOrCine | changed nick to: RexOrCine|away
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22:30 | se6ast1an_ | off to bed, good night
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22:44 | BAndiT1983 | changed nick to: BAndiT1983|away
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23:53 | jhlink | Alright. Thanks for the assist Bertl!! I'll follow up with alexML about that.
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23:53 | jhlink | vup: Cool, cool, cool!
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00:16 | Bertl | you're welcome!
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00:27 | Bertl | off for now ... bbl
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00:27 | Bertl | changed nick to: Bertl_oO
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