#apertus IRC Channel Logs

apurvanandan[m]:, aSobhy: any news on the BER testing front?

Bertl: I am trying really hard, working day and night, to make it work. Current status is ABCDABCDABCD... type data is received correctly, but ABCDEFGHABCDEFGH... type is not

I have made a complete simulation model of both Transmitter and Receiver together and trying to figure out where does the things go wrong :/

sure

For what type of data will you want to see that?

Ok fine, just two minutes

Sorry in 10 minutes

Sorry, I had to reverse the changes in code I made. Here are the two dumps

ACBDDEFGHH types : https://pastebin.com/UBLeiQWS

1+2 columns ie concat we have decoded word

so the first data column will always be 0, yes?

Yes XD

and what data do we 'expect' for both cases?

encoded words are written as per abcdefghij ( not standard abcdeifhj)

The data is written ABCDD in ABCD case, and ABCDDEFGHH in ABCDEFGH case as I used 75 MHz clock to prevent the handling of delay in decoding

The 75 Mhz clock gets converted to 60MHz after the selection in 8 to 10 gearing

https://github.com/apurvanandan1997/BER_measurement/blob/master/MachXO2/Receiver/deserializer8_1.vhd#L108

why is there a point where no word is output?

you generate 8bit words at sclk rate as far as I can tell

Yes then I generate data_rdy signal which is the clock on which data needs to be sampled

so where is the point where you have no code?

on Line 141, we don't assign the decoder's out to par_data signal(output signal)

the question is why?

there is a fixed clock rate at which data (8bit) is generated

and the serializer which outputs the 10bit as serial stream

and fed into the decoder, which converts the 10bit into 8bit

so where does the 'leave out one clock cycle' stuff come in?

okay, that makes sense, you get 4:5 ratio here, but why does that affect the output?

Because 8B/10B decoder takes a clock cycle,so the decoded and encoded word have a difference of a clock cycle in them and if skipped the clock that particular encoded word will be skipped

so if you register the 10bit with SCLK, you have encoded and decoded values at the same clock cycle

so the duplicates come from feeding the debug FIFO on every cycle

Yes exactly

now where does the 75MHz you mentioned come from?

From 8:1 gearing of 300MHz clock

Basically there is no 60MHz clock, it is just 75 MHz clock with a single clock pulse removed every 5 cycles

how to do that?

and the second part you would do in your receiver or with a sed/gawk script

Yes ok

*Sending

off for now ... bbl

apurvanandan[m]: any news?

So I have a good place to debug and I and I am debugging through it

means at the deserializer?

DDR gearing

double check any timing constraints

Ahh, I am checking that

Is there any bnefit of that?

the name of the bits originates from the way the encoding works

i.e. you have a 5/6 and 3/4 encoding

the i and j are the 'additional' bits generated (parity)

Hello Bertl sorry for that delay

and their are some doubts I have:

can't think of any

we did flash on Zynq in our session

return to the first question :)

you need to transfer any debug data via the PIC

off to bed, good night

the PIC is connected communicat with the mach wit jtag right ?

you could use it for SPI or I2C or even UART data transmissions

for example via UART, which can be directly received by a Zynq peripherial

actually I'm going to read the chat we had before to remember again.

Bertl_oO: Yes Bertl trying with full efforts

Bertl how do we add timing constraints to internal signals/clocks?

Something strange is happening, when the link is trained, the words are sampled correctly say 1BC but after some time they get wrong by one bit ie become 1BD

Hey Bertl, Whar should be the delay update frequency between the clock and data?