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#apertus IRC Channel Logs

2019/07/24

Timezone: UTC


03:04
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Nira
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04:13
Bertl_oO
off to bed now ... have a good one everyone!
04:13
Bertl_oO
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Bertl_zZ
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12:27
Bertl
morning folks!
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13:35
Bertl
apurvanandan[m]:, aSobhy: any news on the BER testing front?
15:41
BAndiT1983|away
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BAndiT1983
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se6astian
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16:22
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16:29
apurvanandan[m]
Bertl: I am trying really hard, working day and night, to make it work. Current status is ABCDABCDABCD... type data is received correctly, but ABCDEFGHABCDEFGH... type is not
16:29
Bertl
do we have 10bit debug output yet?
16:29
apurvanandan[m]
I have made a complete simulation model of both Transmitter and Receiver together and trying to figure out where does the things go wrong :/
16:30
apurvanandan[m]
Yes, do you want to see?
16:30
Bertl
sure
16:31
apurvanandan[m]
Yes sending, I am not able to comprehend anything from that
16:31
apurvanandan[m]
For what type of data will you want to see that?
16:31
Bertl
both if possible
16:32
apurvanandan[m]
Ok fine, just two minutes
16:47
Nira
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16:51
apurvanandan[m]
Sorry in 10 minutes
16:56
Bertl
looks more like 25+ minutes to me ... :)
17:34
apurvanandan[m]
Sorry, I had to reverse the changes in code I made. Here are the two dumps
17:34
apurvanandan[m]
ABCDDACBDD types : https://pastebin.com/GEwB4jnb
17:35
apurvanandan[m]
ACBDDEFGHH types : https://pastebin.com/UBLeiQWS
17:35
Bertl
okay, what do I see (columns) this time?
17:36
apurvanandan[m]
1+2 columns ie concat we have decoded word
17:36
apurvanandan[m]
3+4 columns concatenated we have encoded words
17:36
Bertl
so the first data column will always be 0, yes?
17:37
apurvanandan[m]
I wasn't able to infer much so I switched two simulations
17:37
apurvanandan[m]
Yes XD
17:37
apurvanandan[m]
The encoded words are also correct in ABCDABCD case
17:38
Bertl
and what data do we 'expect' for both cases?
17:38
Bertl
because there are duplicates in both dumps on the decoded words
17:38
apurvanandan[m]
encoded words are written as per abcdefghij ( not standard abcdeifhj)
17:40
Bertl
so you are sending A5, 2C, 43, D3, D3 in a loop in the first case?
17:40
apurvanandan[m]
The data is written ABCDD in ABCD case, and ABCDDEFGHH in ABCDEFGH case as I used 75 MHz clock to prevent the handling of delay in decoding
17:40
apurvanandan[m]
sent a long message: < https://matrix.org/_matrix/media/v1/download/matrix.org/nKyeCCEwyeJmwBmlkSPBvvtt >
17:41
apurvanandan[m]
sent a long message: < https://matrix.org/_matrix/media/v1/download/matrix.org/mHnQSmLpSKFeKfgHJvACkvGO >
17:41
Bertl
what is that 75MHz stuff about? please elaborate
17:42
apurvanandan[m]
The 75 Mhz clock gets converted to 60MHz after the selection in 8 to 10 gearing
17:42
Bertl
please show code and explain
17:43
apurvanandan[m]
https://github.com/apurvanandan1997/BER_measurement/blob/master/MachXO2/Receiver/deserializer8_1.vhd#L108
17:44
apurvanandan[m]
We want to miss a clock when no word is output, so that we use that later for make 10bit word
17:45
Bertl
why is there a point where no word is output?
17:45
apurvanandan[m]
hmm?
17:45
Bertl
you generate 8bit words at sclk rate as far as I can tell
17:46
Bertl
you convert them to 10bit words with the encoder
17:46
apurvanandan[m]
Yes then I generate data_rdy signal which is the clock on which data needs to be sampled
17:46
Bertl
that gives you 10bit words at sclk rate
17:47
Bertl
so where is the point where you have no code?
17:47
Bertl
s/code/code word/
17:48
apurvanandan[m]
on Line 141, we don't assign the decoder's out to par_data signal(output signal)
17:49
apurvanandan[m]
Also , Line 190, data output clock is disabled for a cycle
17:49
Bertl
the question is why?
17:50
Bertl
I do not see why you would handle any clock cycle different than all the others
17:50
Bertl
there is a fixed clock rate at which data (8bit) is generated
17:50
Bertl
and the same clock rate is the rate at which the 8b10b encoder runs at
17:51
Bertl
and the serializer which outputs the 10bit as serial stream
17:51
Bertl
on the other end, the 10bit stream is deserialized at the same clock again
17:51
Bertl
and fed into the decoder, which converts the 10bit into 8bit
17:51
Bertl
again at the same clock rate, on every clock cycle
17:52
Bertl
so where does the 'leave out one clock cycle' stuff come in?
17:53
apurvanandan[m]
It is because DDRX4 does 8:1 gearing not 10:1.
17:54
Bertl
okay, that makes sense, you get 4:5 ratio here, but why does that affect the output?
17:55
Bertl
and where does the 75MHz come into play?
17:56
apurvanandan[m]
Because 8B/10B decoder takes a clock cycle,so the decoded and encoded word have a difference of a clock cycle in them and if skipped the clock that particular encoded word will be skipped
17:57
apurvanandan[m]
So for making the dump I printed the decoded word twice using sclk clock.
17:57
Bertl
so if you register the 10bit with SCLK, you have encoded and decoded values at the same clock cycle
17:58
apurvanandan[m]
Otherwise sclk isn't used
17:58
Bertl
so the duplicates come from feeding the debug FIFO on every cycle
17:58
Bertl
not just on cycles where the data is valid?
17:59
apurvanandan[m]
Yes exactly
17:59
Bertl
okay, so that explains this, not sure why you would do that, but okay
18:00
Bertl
now where does the 75MHz you mentioned come from?
18:00
Bertl
(last time you were working with 60MHz for sclk)
18:00
apurvanandan[m]
From 8:1 gearing of 300MHz clock
18:01
Bertl
ah, so you changed that because of the serializer
18:01
apurvanandan[m]
Basically there is no 60MHz clock, it is just 75 MHz clock with a single clock pulse removed every 5 cycles
18:02
Bertl
okay, then let's get rid of the 'invalid' data and output the 10bit values as one 12bit hex
18:04
apurvanandan[m]
how to do that?
18:10
Bertl
well, the first part you do by only sending valid data to the FIFO
18:10
Bertl
and the second part you would do in your receiver or with a sed/gawk script
18:11
apurvanandan[m]
Next part by printing correctly
18:11
apurvanandan[m]
Yes ok
18:14
apurvanandan[m]
Doing as soon as possible
18:14
apurvanandan[m]
*Sending
18:19
apurvanandan[m]
(Having my dinner)
18:25
Bertl
off for now ... bbl
18:25
Bertl
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19:09
BAndiT1983|away
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19:34
se6astian|away
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20:29
Bertl_oO
apurvanandan[m]: any news?
20:30
apurvanandan[m]
I found that errored values were same as being shown on my simulation model I made
20:31
apurvanandan[m]
So I have a good place to debug and I and I am debugging through it
20:31
apurvanandan[m]
In post map and route simulation, I see that the values are sampled wrong at the very first step
20:33
Bertl_oO
means at the deserializer?
20:33
apurvanandan[m]
Yes
20:33
apurvanandan[m]
DDR gearing
20:34
Bertl_oO
which probably means that the serial data has an incorrect phase relation to the clock
20:35
Bertl_oO
double check any timing constraints
20:35
apurvanandan[m]
I see
20:36
RexOrCine|away
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20:39
Bertl_oO
but it could also be related to the word alignment
20:40
apurvanandan[m]
Ahh, I am checking that
21:01
apurvanandan[m]
Bertl_oO Does the 10 bit encoded word needs to be transferred as abcdeifhj ie 'i' before 'f'?
21:01
apurvanandan[m]
Is there any bnefit of that?
21:08
Bertl_oO
hmm?
21:09
Bertl_oO
the name of the bits originates from the way the encoding works
21:09
apurvanandan[m]
Sorry, got confused
21:10
Bertl_oO
i.e. you have a 5/6 and 3/4 encoding
21:10
apurvanandan[m]
Yes I understood
21:10
Bertl_oO
the i and j are the 'additional' bits generated (parity)
21:18
Nira|away
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21:31
aSobhy
Hello Bertl sorry for that delay
21:31
aSobhy
I fixed the word alignment issue from a while and making a final test to run on the beta tonight I hope
21:31
aSobhy
and their are some doubts I have:
21:32
aSobhy
how to get the final register from the mach is their any script ready I can use ?
21:33
Bertl_oO
can't think of any
21:33
aSobhy
as I remember we don't discussed how to flash on zynq
21:33
Bertl_oO
we did flash on Zynq in our session
21:35
aSobhy
I think no I'll check again
21:36
aSobhy
return to the first question :)
21:36
Bertl_oO
as I said, there is nothing ready to 'read' anything from the MachXO2
21:37
Bertl_oO
you need to transfer any debug data via the PIC
21:39
aSobhy
mmmm I didn't catch the last one
21:39
se6astian
off to bed, good night
21:39
se6astian
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21:40
BAndiT1983
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21:41
Bertl_oO
if you want to inspect anything in the MachXO2, you need to go through the PIC controlling the MachXO2
21:41
aSobhy
the PIC is connected communicat with the mach wit jtag right ?
21:41
Bertl_oO
yes, but it has a number of other connections as well
21:42
Bertl_oO
you could use it for SPI or I2C or even UART data transmissions
21:43
Bertl_oO
the other (probably simpler option) is to use a dedicated LVDS pair to send (debug) data from the MachXO2 to the Zynq
21:43
Bertl_oO
for example via UART, which can be directly received by a Zynq peripherial
21:45
Bertl_oO
btw, about 1 day and 20 hours left to get BER testing sorted :)
21:46
aSobhy
actually I'm going to read the chat we had before to remember again.
21:46
aSobhy
Is the time enough?
21:47
apurvanandan[m]
Bertl_oO: Yes Bertl trying with full efforts
21:48
aSobhy
I'm working hard
22:11
apurvanandan[m]
Bertl how do we add timing constraints to internal signals/clocks?
22:42
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23:17
apurvanandan[m]
Bertl_oO: are you available?
23:18
apurvanandan[m]
Something strange is happening, when the link is trained, the words are sampled correctly say 1BC but after some time they get wrong by one bit ie become 1BD
23:20
apurvanandan[m]
No significant change is occuring at that time when this error occurs, it seems to happen by itself
23:49
apurvanandan[m]
Hey Bertl, Whar should be the delay update frequency between the clock and data?
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RexOrCine
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