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03:47 | Bertl | off to bed now ... have a good one everyone!
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08:31 | eppisai[m] | good morning, folks! :)
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09:10 | se6ast1an | good day
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13:00 | Bertl | morning folks!
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16:00 | se6ast1an | MEETING TIME, welcome everyone!
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16:00 | se6ast1an | who is here?
| 16:00 | vup | is here
| 16:00 | eppisai[m] | is here!
| 16:00 | Bertl | is here ...
| 16:00 | anuejn | is here
| 16:01 | tpw_rules | is here
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16:01 | se6ast1an | Great!
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16:02 | se6ast1an | So in general it is expected of all team members and GSoC students to participate at these weekly meeting, I will also send a reminder email to all other students who did not pick up the habbit yet
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16:02 | Dest123 | Dest123 is here
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16:02 | vnksnkr | is here
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16:03 | se6ast1an | if you cant make it let us know in advance, if you supply a brief summary of your last week activity I can share that with others in your absence
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16:03 | se6ast1an | as suggested by vup I would like to also discuss with students/mentors about a separate irc channel just for gsoc
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16:04 | se6ast1an | we used #gsoc2020 last year but to not create a new one every year what about #apertus-gsoc?
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16:04 | tpw_rules | what goes on in that channel specifically? administrative stuff?
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16:04 | vup | works for me, I guess we want to do it on libera?
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16:04 | tpw_rules | ^
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16:04 | se6ast1an | yes libera brings us to the next big topic
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16:04 | tpw_rules | (i will be on libera later this week)
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16:04 | bluez | \me is here
| 16:04 | bluez | is here
| 16:04 | anuejn | votes also in favr of ibera
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16:05 | se6ast1an | tpw_rules: everything gsoc related that for some reason participants are not comfortable doing here on main chan
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16:05 | se6ast1an | can be administrative stuff or deep task related technical stuff between mentor/student
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16:05 | se6ast1an | in any case you can discuss all that here, just if you prefer not to thats the channel then for it #apertus-gsoc
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16:05 | se6ast1an | so libera:
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16:06 | se6ast1an | in case you have not seen it yet:
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16:06 | se6ast1an | https://hackaday.com/2021/05/20/freenode-debacle-prompts-staff-exodus-new-network/
| 16:06 | metal_dent[m] | will move to libera soon
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16:06 | se6ast1an | https://fuchsnet.ch/freenode-resign-letter.txt
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16:06 | se6ast1an | freenode is soon to be abandoned :)
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16:06 | se6ast1an | we already have moved #apertus to libera.chat server
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16:07 | anuejn | but, I would also ask everyone to do things that can be done in the main channel - do them in the main channel
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16:07 | anuejn | as it is logged and can be searched afterwards
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16:07 | se6ast1an | currently we operate in both "worlds"
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16:07 | se6ast1an | but its just a matter of time when we will move there entirely
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16:07 | Bertl | let's make the move quickly
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16:08 | se6ast1an | there is no rush/urgency but also no reason to stay here longer than necessary
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16:08 | Bertl | we can leave a topic and maybe some log bot behind
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16:08 | se6ast1an | so everyone should register accounts/nicks there already and join the respective channels, there is no reason not to at this point :)
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16:08 | danieeel | it would be good to forward everybody to the new place, so just make a hard switch, to avoid duplicate rooms
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16:09 | danieeel | something like lock the chan for posting, and autoreply by a bot?
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16:09 | danieeel | changed nick to: danieel
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16:09 | tpw_rules | i have seen rumors that the new freenode staff are willing to take over migrated channels on this network, so it would be good to leave something here
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16:09 | se6ast1an | yes, a quick switch would be prefered but with almost 50 nicks in here I also dont want to leave people behind
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16:10 | vup | To help agains splitting up the channels we probably just want to set +m on the freenode channels soon
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16:10 | danieel | a copy/paste sync bot? :)
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16:11 | se6ast1an | we can target to hold the next week meeting on libera already
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16:11 | se6ast1an | I think a week would be a good timeframe to reach most people
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16:11 | se6ast1an | another topic raised recently is a separate GSoC meeting after the normal meeting
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16:12 | se6ast1an | where students/mentors can interact as desired
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16:12 | se6ast1an | where the normal meeting should focus on brief reports/next steps from everyone
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16:12 | se6ast1an | if thats alright for mentors students I would like to also make that a habbit
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16:12 | se6ast1an | 1h after normal meeting
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16:13 | se6ast1an | UTC 17:00 that is every monday
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16:13 | tpw_rules | i like the idea. is it necessary to have it at its own time?
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16:13 | se6ast1an | not really as everyone is around anyways in the best case
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16:14 | se6ast1an | but should still help as a general guideline
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16:14 | Bertl | so let's just call it 'after the regular meeting' :)
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16:14 | se6ast1an | also fine :)
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16:15 | se6ast1an | ok quick round of updates from everyone
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16:15 | se6ast1an | vup any news from you?
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16:15 | vup | sure
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16:17 | se6ast1an | please share :)
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16:17 | vup | yep, trying to :)
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16:17 | vup | just crashed my browser by pasting a link into it :)
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16:17 | vup | Ok
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16:18 | vup | So I mostly worked on two things, I continued working on creating a prototype of the RPC protocol for the new control daemon.
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16:18 | vup | This is not yet finished, but I think I have most of the basic concepts now thought out and should have a working prototype soon.
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16:19 | vup | Furthermore discussions with anuejn about the current state of the nmigen gateware brought me to think about that more again aswell.
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16:20 | vup | Currently there are some rather magic and or unpleasent parts of it.
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16:20 | vup | There are mostly summarized here: https://github.com/apertus-open-source-cinema/naps/discussions/11
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16:21 | vup | The first thing I decided to tackle was the elaboration order problem.
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16:21 | vup | This occurs in a couple of places, but we can take the integrated logic analyzer as an example:
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16:22 | vup | In nmigen module can be composed of submodules.
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16:22 | vup | And a module is turned into its equivalent statements by the `elaborate` method.
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16:23 | vup | For the integrated logic analyzer we want to be able to add probes all over the design and then in the end connect them up to some trigger logic, sample memory and readout logic.
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16:23 | vup | So for this to work well, the ILA would have to be elaborated after all other modules.
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16:23 | vup | (Because all other modules could in theory add probes)
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16:24 | vup | But because nmigen will elaborate submodules only after the main module is elaborated this is very hard.
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16:24 | vup | So the currently idea is to create a thin layer above nmigen, which has a two phase elaboration
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16:25 | vup | The first phase is like the normal nmigen elaborate method, where you can add statements, submodules, etc.
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16:25 | vup | But additionally there is a second phase which is called after all the submodules are (recursively) elaborated, where one can add additional statements.
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16:25 | vup | This makes adding something like the integrated logic analyzer quite easy.
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16:25 | vup | You can find a current design prototype here: https://codimd.niemo.de/6yhlGdaNT8e2F9gfIPuHeQ?view
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16:27 | vup | The goal is, to further extend this prototype to adequately address all the pain points linked above, you can find some general ideas and notes below the code in the linked prototype
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16:27 | vup | Sorry for this wall of text :)
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16:27 | vup | Thats it from me this week.
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16:28 | se6ast1an | many thanks, very interesting but mostly hard to understand from an outside perspective
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16:28 | se6ast1an | or at least from me :)
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16:29 | se6ast1an | eppisai[m]: your up next
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16:29 | vup | Yeah, sorry, its probably easier to understand if you are atleast a bit familiar with nmigen (like tpw_rules or Bertl :)
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16:29 | eppisai[m] | Hello Everyone!
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16:30 | eppisai[m] | So, last week I declared a transition framebuffer in linker script and was analysing the linker script as to why their where two different framebuffer memory segment in kseg0 and kseg1
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16:32 | eppisai[m] | upon discussing with BAandiT1983, bootloader framebuffer is not being used currently and was mostly declared if wanted to added transition in future..
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16:32 | eppisai[m] | So have been doing that..
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16:32 | eppisai[m] | and found a new version of xc32
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16:32 | BAndiT1983 | as bootloader framebuffer is not used, it won't be required there, only UART or USB connection, so no need to bother with such details
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16:33 | eppisai[m] | oh.. was wondering.. since framebuffer manipulations are done in firmware itself
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16:33 | eppisai[m] | will keep this mind :)
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16:33 | eppisai[m] | so, continuing..
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16:33 | BAndiT1983 | bootloader will take the role of BIOS and data transfer
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16:35 | eppisai[m] | had just adjusted the current makefile for xc32 v3.00 and read about the new features.. seems very exciting (gcc now 8.3.1) that means c++11 is supported
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16:35 | eppisai[m] | BAndiT1983: ohk..
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16:35 | eppisai[m] | so, thats it..
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16:35 | eppisai[m] | Thanks :)
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16:36 | eppisai[m] | https://ww1.microchip.com/downloads/en/DeviceDoc/xc32-v3.00-full-install-release-notes.html
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16:36 | se6ast1an | many thanks, the changes for updated compiler have already been merged in github repo
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16:36 | se6ast1an | anuejn: please share your progress update next
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16:36 | BAndiT1983 | but it still requires testing on real hardware!
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16:37 | anuejn | I worked mainly on the nmigen gateware since I last reported.
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16:37 | anuejn | While trying to write a mipi-dsi transmitter I really missed some debugging infrastructure.
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16:37 | anuejn | So I wrote an integrated-logic-analyzer (ILA) and some nescessary support infrastructure.
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16:37 | eppisai[m] | BAndiT1983: yes, will do so after todays meet. :)
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16:37 | anuejn | * It is now possible to communicate constants from bitstream generation time to runtime (eg. configuration).
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16:38 | Bertl | BAndiT1983: speaking of hardware, we should check if the EF can be used for the remote setup or alternatively we have to replace that
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16:38 | anuejn | * There Is now a Memory that can map to block ram on the fpga and can be read / written to by the python driver code. (in addition to the already existing CSRs)
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16:38 | anuejn | * There are cores for generating / reading PacketizedStreams from / to the driver
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16:39 | anuejn | * The ILA itself finally has many handy features like pretrigger, support for decoding FSM states to strings and writing VCD files.
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16:39 | anuejn | Also I renamed the 'nmigen-gateware' repo to 'naps' to be the same as the python package.
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16:39 | anuejn | Thats it from my side :)
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16:40 | se6ast1an | lots of progress, great
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16:40 | se6ast1an | many thanks
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16:40 | se6ast1an | Dest123: your turn please
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16:41 | Dest123 | I started working on the CMV12K output channels this week
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16:41 | Dest123 | I'm currently working on the data training over the channels
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16:42 | Dest123 | that's it for me :)
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16:43 | se6ast1an | many thanks!
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16:43 | se6ast1an | vnksnkr: any news from your side?
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16:44 | vnksnkr | I've been mostly reading a few datasheets as well as the wiki this week
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16:44 | vnksnkr | I did get started with a pulse generator for sending the signals to the Remote.
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16:45 | vnksnkr | That's it nothing else from my side :)
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16:45 | se6ast1an | sending signals to the remote, please elaborate
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16:46 | vnksnkr | sure so I need to send signals to simulate the button presses on the Remote for testing
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16:48 | se6ast1an | right, just had to read up on your task to remind myself of the underlying hardware: https://lab.apertus.org/T1233
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16:48 | vnksnkr | So one challenge is to simulate the bouncing patterns and I've been working on a pulse generator that would generate random pulses within a time interval
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16:48 | se6ast1an | the hardware is already in place in the remote access setup I assume Bertl ?
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16:49 | Bertl | yes, but it has had only basic testing so far
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16:50 | se6ast1an | right
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16:50 | se6ast1an | anyone else who wants to share anything (I will share next and leave the closing words to Bertl as its tradition already)?
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16:51 | se6ast1an | I want to focus on getting the JTAG hardware debugger up and running with the AXIOM Remote
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16:52 | se6ast1an | I will need some guidance for that from Bertl but would document any findings so the nxt folks should get it setup much quicker already
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16:52 | se6ast1an | last week tele/factoryhub reported that the last stage of hardware production is ongoing with the soldering of the image sensors sockets
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16:52 | se6ast1an | everything else has been completed
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16:53 | se6ast1an | I did not get a heads up on it being finished yet but since today is a holiday (at least here) I will inquire again for a status update tomorrow
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16:53 | se6ast1an | all other boards have been received and scanned with 1200DPI for placement documentation
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16:53 | se6ast1an | all boards together will be handed over to Bertl as next step, hopefully this week
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16:54 | se6ast1an | on another front I have done pretty much everything to get the nvme ssd performance on the rock pi 4 to meaningful levels without success
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16:54 | se6ast1an | I get > 1 Gbit/s throughput writing zeros
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16:54 | se6ast1an | but for random data the maximum was around 290MB/s
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16:55 | se6ast1an | the same nvme ssd connected to a fast laptop over USB3 achieved ~400MB/s in exactly the same benchmark
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16:55 | se6ast1an | maybe you have seen the email today from Charlie from https://andahammer.com/
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16:56 | se6ast1an | I hope he can provide some new input with similar hardware (NanoPi M4V2)
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16:56 | se6ast1an | combined with nvme ssd
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16:56 | se6ast1an | if anyone of you have a nvme ssd lying around and any SBC with nvme ssd compatiblility let me know
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16:57 | se6ast1an | lastly BAndiT1983 and me worked on the online 3d cad viewer in the last week with nice progress to showcase
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16:57 | se6ast1an | https://apertus-open-source-cinema.github.io/cad-3d-viewer/prototype/
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16:58 | se6ast1an | BAndiT1983: implemented screen space reflections (not perfect yet, bit blocky and distorted on some surfaces)
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16:58 | se6ast1an | but IMO looking great already
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16:58 | se6ast1an | I added a multi material assembly (labeled "Assembly Test") that you can already try online
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16:59 | BAndiT1983 | *added, not implemented (although thinking of adding own implementation based on newer algorithms)
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16:59 | BAndiT1983 | *meant SSR
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16:59 | se6ast1an | and emount and cap bottom also show a location image now that displays where this part is located in the camera assembly
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16:59 | Bertl | opacity looks like it controls the reflectiveness here
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16:59 | BAndiT1983 | it's called opacity in SSRPass, so kept the name
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16:59 | Bertl | but it is impressive how good it loops
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16:59 | Bertl | *looks
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17:00 | se6ast1an | thanks :D
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17:00 | se6ast1an | next steps are a UI overhaul with screendesign here: https://paste.pics/3f0e34773ff7099ae46e98d2caaabf67
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17:00 | se6ast1an | in general I am not a big fan of dark UIs so thinking of the same in a bright design (just inverted colors ) : https://paste.pics/abde01cdc389d719899b3448f8719843
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17:01 | se6ast1an | what are your thoughts on bright vs dark ?
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17:01 | se6ast1an | BAndiT1983 already promised to add a switch to change themse easily
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17:01 | se6ast1an | but I think a general idea of peopels opinion would also be nice
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17:02 | Bertl | I like dark themes ;)
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17:02 | se6ast1an | noted :)
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17:02 | metal_dent[m] | Dark \o/
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17:02 | tpw_rules | i like light themes
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17:02 | eppisai[m] | I like the idea of giving user the option.. that is dark and light toggle button
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17:02 | bluez | dark always :)
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17:03 | BAndiT1983 | some dark souls here
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17:03 | vnksnkr | :)
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17:03 | eppisai[m] | :D :D
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17:03 | se6ast1an | thanks, seems like a toggle option is indeed the best way to go :)
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17:04 | bluez | hehe.. yep toggle will be best i think
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17:04 | se6ast1an | we will continue tweaking the materials as well and the GUI
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17:04 | se6ast1an | I think thats it from my side
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17:04 | se6ast1an | Bertl: your honor?
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17:04 | Bertl | thanks
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17:05 | Bertl | well, not too much happened here this week, I mainly spent the time on getting the remote setup up and running
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17:05 | Bertl | we will do a session after this meeting (after a short break) for our 2021 students
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17:06 | Bertl | I also did some tests on the gateware side regarding splitting up the input and the output pipeline
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17:07 | Bertl | which seems for me the way to go in the future
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17:07 | Bertl | except for helping students here and there that's it for the last week
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17:08 | se6ast1an | many thanks!
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17:08 | se6ast1an | anyone else with anything to share/report/discuss?
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17:09 | se6ast1an | right then! MEETING CONCLUDED!
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17:10 | se6ast1an | feel free to start the task related discussions here after your short break
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17:10 | Bertl | okay, let's take a 20min break, and continue at 19:30 with the remote setup on #apertus-gsoc
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17:13 | Bertl | (let's use the libera.chat network for that ;)
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