#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

morning folks!

MEETING TIME, welcome everyone!

So in general it is expected of all team members and GSoC students to participate at these weekly meeting, I will also send a reminder email to all other students who did not pick up the habbit yet

is here

as suggested by vup I would like to also discuss with students/mentors about a separate irc channel just for gsoc

what goes on in that channel specifically? administrative stuff?

^

(i will be on libera later this week)

tpw_rules: everything gsoc related that for some reason participants are not comfortable doing here on main chan

in any case you can discuss all that here, just if you prefer not to thats the channel then for it #apertus-gsoc

in case you have not seen it yet:

freenode is soon to be abandoned :)

but, I would also ask everyone to do things that can be done in the main channel - do them in the main channel

currently we operate in both "worlds"

let's make the move quickly

we can leave a topic and maybe some log bot behind

it would be good to forward everybody to the new place, so just make a hard switch, to avoid duplicate rooms

yes, a quick switch would be prefered but with almost 50 nicks in here I also dont want to leave people behind

a copy/paste sync bot? :)

I think a week would be a good timeframe to reach most people

where students/mentors can interact as desired

if thats alright for mentors students I would like to also make that a habbit

UTC 17:00 that is every monday

not really as everyone is around anyways in the best case

so let's just call it 'after the regular meeting' :)

ok quick round of updates from everyone

sure

yep, trying to :)

Ok

This is not yet finished, but I think I have most of the basic concepts now thought out and should have a working prototype soon.

Currently there are some rather magic and or unpleasent parts of it.

The first thing I decided to tackle was the elaboration order problem.

In nmigen module can be composed of submodules.

For the integrated logic analyzer we want to be able to add probes all over the design and then in the end connect them up to some trigger logic, sample memory and readout logic.

(Because all other modules could in theory add probes)

So the currently idea is to create a thin layer above nmigen, which has a two phase elaboration

But additionally there is a second phase which is called after all the submodules are (recursively) elaborated, where one can add additional statements.

You can find a current design prototype here: https://codimd.niemo.de/6yhlGdaNT8e2F9gfIPuHeQ?view

Sorry for this wall of text :)

many thanks, very interesting but mostly hard to understand from an outside perspective

eppisai[m]: your up next

Hello Everyone!

upon discussing with BAandiT1983, bootloader framebuffer is not being used currently and was mostly declared if wanted to added transition in future..

and found a new version of xc32

oh.. was wondering.. since framebuffer manipulations are done in firmware itself

so, continuing..

had just adjusted the current makefile for xc32 v3.00 and read about the new features.. seems very exciting (gcc now 8.3.1) that means c++11 is supported

so, thats it..

https://ww1.microchip.com/downloads/en/DeviceDoc/xc32-v3.00-full-install-release-notes.html

anuejn: please share your progress update next

I worked mainly on the nmigen gateware since I last reported.

So I wrote an integrated-logic-analyzer (ILA) and some nescessary support infrastructure.

* It is now possible to communicate constants from bitstream generation time to runtime (eg. configuration).

* There Is now a Memory that can map to block ram on the fpga and can be read / written to by the python driver code. (in addition to the already existing CSRs)

* The ILA itself finally has many handy features like pretrigger, support for decoding FSM states to strings and writing VCD files.

Thats it from my side :)

many thanks

I started working on the CMV12K output channels this week

that's it for me :)

vnksnkr: any news from your side?

I did get started with a pulse generator for sending the signals to the Remote.

sending signals to the remote, please elaborate

right, just had to read up on your task to remind myself of the underlying hardware: https://lab.apertus.org/T1233

the hardware is already in place in the remote access setup I assume Bertl ?

right

I want to focus on getting the JTAG hardware debugger up and running with the AXIOM Remote

last week tele/factoryhub reported that the last stage of hardware production is ongoing with the soldering of the image sensors sockets

I did not get a heads up on it being finished yet but since today is a holiday (at least here) I will inquire again for a status update tomorrow

all boards together will be handed over to Bertl as next step, hopefully this week

I get > 1 Gbit/s throughput writing zeros

the same nvme ssd connected to a fast laptop over USB3 achieved ~400MB/s in exactly the same benchmark

I hope he can provide some new input with similar hardware (NanoPi M4V2)

if anyone of you have a nvme ssd lying around and any SBC with nvme ssd compatiblility let me know

https://apertus-open-source-cinema.github.io/cad-3d-viewer/prototype/

but IMO looking great already

*added, not implemented (although thinking of adding own implementation based on newer algorithms)

and emount and cap bottom also show a location image now that displays where this part is located in the camera assembly

it's called opacity in SSRPass, so kept the name

*looks

next steps are a UI overhaul with screendesign here: https://paste.pics/3f0e34773ff7099ae46e98d2caaabf67

what are your thoughts on bright vs dark ?

but I think a general idea of peopels opinion would also be nice

noted :)

i like light themes

dark always :)

:)

thanks, seems like a toggle option is indeed the best way to go :)

we will continue tweaking the materials as well and the GUI

Bertl: your honor?

well, not too much happened here this week, I mainly spent the time on getting the remote setup up and running

I also did some tests on the gateware side regarding splitting up the input and the output pipeline

except for helping students here and there that's it for the last week

anyone else with anything to share/report/discuss?

feel free to start the task related discussions here after your short break

(let's use the libera.chat network for that ;)