| 23:28 | Bertl_oO | off to bed now ... have a good one everyone!
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| 05:30 | Bertl | morning folks!
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| 06:00 | metal_dent[m] | morning Bertl !
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| 07:29 | se6ast1an | good morning
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| 07:57 | bluez_[m] | Good morning everyone!
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| 08:33 | bluez_[m] | Bertl: Hey! So I did some research. I needed to ask a few questions...
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| 08:33 | Bertl | sure, go ahead
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| 08:36 | bluez_[m] | ok so... the driver I am going to make will use i2c to send commands to the pic? The pic, in response to these commands, will upload the "gateware" bitstream into macxo2's sram?
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| 08:37 | bluez_[m] | is this correct so far?
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| 08:38 | Bertl | yes
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| 08:39 | bluez_[m] | okay... so where is the gateware stored initially?
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| 08:39 | Bertl | on the SD card of the Axiom Beta
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| 08:40 | bluez_[m] | okay...so do we send that data too to the pic or the pic just responds to the command from main board and copies the gateware from sd card to the fpga?
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| 08:41 | Bertl | the PIC has no access to the SD card, so the data is sent over the I2C bus
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| 08:42 | bluez_[m] | ohh okay... so how do we retrieve the gateware from sdcard?
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| 08:42 | Bertl | for example with 'cat'
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| 08:43 | Bertl | as in 'cat /path/to/machxo2-gateware.bin >/dev/rfe'
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| 08:43 | bluez_[m] | i mean how will our driver do that? we need a script to first retrive that data?
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| 08:43 | Bertl | or alternatively the driver can request the firmware from a specific location
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| 08:44 | Bertl | (like it is done with other firmwares recently)
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| 08:44 | bluez_[m] | location in memory?
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| 08:44 | Bertl | filesystem
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| 08:45 | bluez_[m] | ohh okay
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| 08:47 | bluez_[m] | also if we are using i2c then why does the task mention "some kind of upload interface (JTAG, I2C, SPI)"
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| 08:47 | Bertl | that's the interface between PIC and MachXO2
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| 08:48 | Bertl | Zynq <-I2C-> PIC <-JTAG-> MachXO2
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| 08:48 | bluez_[m] | ok..how do i do that? the driver only works on the main board which runs linux right?
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| 08:48 | Bertl | correct
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| 08:48 | Bertl | the firmware for the PIC handles the translation
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| 08:48 | bluez_[m] | ohhh ok ok thats clear
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| 08:49 | bluez_[m] | so at first i only need to worry about sending commands to the pic along with gateware?
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| 08:49 | Bertl | yes
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| 08:50 | bluez_[m] | what about the second part "a debug interface (probably JTAG) to interface OpenOCD"
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| 08:51 | Bertl | what about it?
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| 08:52 | bluez_[m] | i mean... firstly, what does "interfacing OpenOCD" mean?
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| 08:53 | Bertl | you know what openocd is?
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| 08:53 | bluez_[m] | all i got is its for on chip debugging
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| 08:53 | bluez_[m] | just like jtag
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| 08:53 | Bertl | yeah, JTAG is the protocol/interface to do all kind of stuff including debugging
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| 08:54 | Bertl | OpenOCD is a software solution to allow access to such an interface via some kind of hardware
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| 08:55 | Bertl | for example, let's say you have a MachXO2 and you want to do some JTAG stuff on it
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| 08:55 | bluez_[m] | okay...
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| 08:55 | Bertl | you hook the jtag port up to some hardware dongle, let's say an FTDI chip
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| 08:56 | bluez_[m] | u mean a jtag programmer?
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| 08:56 | Bertl | then you configure OpenOCD properly and you can do things like retrieving data from the MachXO2
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| 08:56 | Bertl | yes, for example a JTAG programmer
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| 08:58 | Bertl | in our case, the JTAG programmer is the PIC
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| 08:58 | bluez_[m] | i see.... so openocd is a software sitting on the main board running under linux?... but how do we configure it to work "through" i2c to the pic...which than translates to jtag ?
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| 08:58 | bluez_[m] | <Bertl "in our case, the JTAG programmer"> ouuuu... okay makes sense
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| 08:58 | Bertl | well, that's part of the task to figure this out
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| 08:59 | Bertl | i.e. what is the best way to get the interface between OpenOCD and the PIC/JTAG working
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| 08:59 | bluez_[m] | is that related to making a driver??
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| 09:00 | Bertl | yes
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| 09:00 | BAndiT1983 | Bertl: is it similar to LVP approach?
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| 09:00 | bluez_[m] | i see... where can i find more info about how the pic does stuff? Its seems a black box to me right now...
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| 09:00 | Bertl | BAndiT1983: not sure what you mean by that
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| 09:00 | BAndiT1983 | datasheets
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| 09:01 | BAndiT1983 | i mean if the signals for JTAG are generated similar to LVP ones, with toggling pins correctly
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| 09:01 | BAndiT1983 | *-with +like
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| 09:01 | Bertl | yes
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| 09:01 | BAndiT1983 | ok, interesting
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| 09:02 | Bertl | bluez_[m]: we use a PIC16F1718 and documentation can be found here:
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| 09:02 | Bertl | https://www.microchip.com/wwwproducts/en/PIC16F1718
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| 09:03 | Bertl | but unless you want to improve the firmware for the PIC, it is probably fine to consider it a black box device on the I2C bus which can do a few JTAG related tricks
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| 09:03 | bluez_[m] | <Bertl "https://www.microchip.com/wwwpro"> okay thank you!
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| 09:05 | bluez_[m] | Also, one final question, while writing the schedule, how detailed do I need to be? Cuz I am just learning right now I have an idea how it will go...but the details I can figure out while working?
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| 09:05 | BAndiT1983 | weekly-based timeline is mandatory
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| 09:05 | BAndiT1983 | to be able to verify the progress
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| 09:06 | bluez_[m] | <Bertl "but unless you want to improve t"> okay! Although, I needed to find out how the pic is programmed...i.e. what commands it will respond to and in what way...
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| 09:07 | Bertl | that is correct
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| 09:08 | bluez_[m] | <BAndiT1983 "to be able to verify the progres"> oh okay.... I'll share a draft after it is done then... can get your comments...
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| 09:09 | bluez_[m] | Bertl: Okay thanks a lot! It really helped. Working on the proposal then...
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| 09:10 | bluez_[m] | Oh and I more thing I forgot to ask ':D... the environment I need to setup... how am i going to test my code? remotely i guess but how exactly?
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| 09:17 | Bertl | we will provide remote access to an Axiom Beta, i.e. you logon via ssh and can work there
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| 09:18 | bluez_[m] | <Bertl "we will provide remote access to"> okay that works.. thanks again!
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| 09:18 | Bertl | you're welcome!
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| 12:23 | Bertl | off for now ... bbl
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| 15:09 | Dest | hello
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| 15:10 | BAndiT1983 | hi Dest
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| 15:12 | Dest | I've started on VHDL challenge and finished the separate UART & SPI-Master Modules
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| 15:12 | Dest | can someone have a look ?
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| 15:12 | Dest | https://drive.google.com/drive/folders/1Nl2zrLudWy8CafmEpvtH5W5cevLHMGmy?usp=sharing
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| 15:13 | BAndiT1983 | good, but you would have to wait for Bertl_oO, as he is the mentor for VHDL
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| 15:13 | Dest | sure, thank you
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| 17:42 | Bertl_oO | Dest: says I need permission to access ...
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| 18:26 | Dest | oh sorry for that
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| 18:27 | Dest | would you check again now
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| 18:30 | Bertl | needs some formatting
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| 18:31 | Bertl | also it would be beneficial to have a short info how to build and test the project
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| 18:37 | Bertl | Dest46: you also might want to consider getting a proper IRC client instead of the web client
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| 18:38 | Dest | I will find another client
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| 18:38 | Dest | Regarding the formatting, can you elaborate a little more?
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| 18:45 | Bertl | for example proper spacing around expressions
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| 18:46 | Bertl | best take a look at existing code and try to fit in
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| 18:54 | Dest123 | bretl: I've found a better client and I'll start working on your comments
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| 18:54 | Bertl | excellent!
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| 19:27 | Dest123 | Should the SPI-Master send and receive from the UART at the same time?
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| 19:44 | Bertl | doesn't really matter
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| 20:03 | Dest123 | This is how I imagine the bridge should be
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| 20:03 | Dest123 | https://drive.google.com/a/zewailcity.edu.eg/file/d/1hFF7rYAhqarGxgekWEFm-yazuCAqdJ5s/view?usp=drivesdk
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| 20:07 | Bertl | best model some SPI slaves and test it then
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| 20:48 | preetimenghwani[ | sent a long message: < https://matrix.org/_matrix/media/r0/download/matrix.org/JJQRkTWShEyrDEIPaJqervds >
| | 20:50 | Bertl | can't read long messages at the moment
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| 20:51 | preetimenghwani[ | Oh I am really sorry
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| 20:52 | preetimenghwani[ | I have some questions regarding T1130
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| 20:52 | Bertl | let's hear then ..
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| 20:53 | preetimenghwani[ | I understood pixel remapping but how can that help in compaction of data stream
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| 20:54 | preetimenghwani[ | Also how can rearrangement and repacking help in compaction
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| 20:55 | Bertl | the DDR memory is accessed via AXI bus interface
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| 20:55 | Bertl | and to achieve maximum throughput, burst writes are required
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| 20:56 | Bertl | this means that blocks of 64/128 bit need to be sent
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| 20:57 | Bertl | let's say the sensor is operating in 12 bit mode, then the sensel data needs to be rearranged to fit into those 64/128 bit words
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| 20:58 | Bertl | this is what the task description refers to as (re)packing
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| 20:59 | Bertl | the sensel data also does not come as one sensel at a time ... depending on the sensor configuration up to 64 sensel are shifted in in parallel
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| 21:00 | Bertl | as additional complication, those pixel are spread out over one or two lines and thus require rearrangement to be stored in order
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| 21:04 | preetimenghwani[ | By 12 bit mode you mean that pixels store 12 bit data right?
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| 21:05 | Bertl | yes
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| 21:06 | preetimenghwani[ | So the packets will be of size 128*12 and that we need to break into 64/128 bits just confirming
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| 21:07 | Bertl | the sensor has a number of data outputs (up to 64 in the CMV12k case)
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| 21:08 | Bertl | and each data output transmits a sensel (8, 10 or 12 bit) serially
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| 21:09 | Bertl | the sensel are from spaced colums, e.g. 0, 128, 256, ...
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| 21:10 | Bertl | the data is deserialized in parallel and needs to be rearranged into a sequence of 64/128 bit words for storing into DDR memory via the AXI bus
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| 21:12 | Bertl | e.g. for 12bit, and 64bit words, 3 words i.e. a total of 192bit would work
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| 21:16 | preetimenghwani[ | You said each data output transmits a sensel but LVDS outputs transmits 128 pixels at a time
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| 21:17 | preetimenghwani[ | I am sorry for bothering you with silly questions
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| 21:17 | Bertl | did I say that?
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| 21:18 | Bertl | at most 64 sensel are transferred in parallel (for the CMV12k)
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| 21:18 | preetimenghwani[ | Oh okay my bad
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| 21:20 | Bertl | and no problem regarding questions, that's what we are here for at the moment
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| 21:27 | preetimenghwani[ | The task says we need to implement remapping strategies does it mean that we need to modify existing ones with lower gate count?
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| 21:29 | Bertl | there is an existing remapper but it is very limited
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| 21:29 | Bertl | and yes, the goal is to optimize gate count and performance
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| 21:31 | preetimenghwani[ | Very limited in what sense?
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| 21:32 | Bertl | it only handles 12bit and 32 sensel at the moment
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| 21:33 | Dest123 | hey bretl, I was wondering how are challenging tasks going to be evaluated
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| 21:34 | Bertl | depends on the tasks, but in general we review them, provide some feedback, see how the student improves/adapts and draw our conclusions
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| 21:38 | Dest123 | Should tasks supporting additional functionality have a higher acceptance rate?
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| 21:40 | Bertl | if the functionality makes sense in the context and doesn't bloat the implementation unnecessarily, then yes
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| 21:41 | preetimenghwani[ | There are remapping strategies for binning and subsampling we need to improvise the strategiea for both?
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| 21:41 | Bertl | Dest123: note that attention to detail is better than producing tons of code
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| 21:42 | Bertl | the sensor supports a number of 'modes' which affect how the data is transmitted
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| 21:42 | Bertl | i.e. the semantics of the data, not the actual transmission
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| 21:43 | Bertl | switching the mode requires the remapper to accomodate for this, otherwise the data will be out of sequence
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| 21:44 | preetimenghwani[ | By modes you mean 162 or 321 right?
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| 21:45 | preetimenghwani[ | Sorry 32 x 1 or 16x 2
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| 21:45 | Bertl | more the subsampling, binning, windowing and number of output channels
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| 21:52 | preetimenghwani[ | Thanks a lot Bertl that was really helpful!
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| 21:52 | Bertl | you're welcome!
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