#apertus IRC Channel Logs

off to bed now .. have a good one everyone!

so if you have topics that we should cover

let me know

Hi Bertl.

Everythings fine.For the sobel fpga project, I am thinking that there will be four module- a control module (which will be like a master and will monitor the communications from cmos sensor to FPGA) ; the kernel module( which will generate a N*N kernel);a line buffer module and a address control module( to ensure that correct pixels are stored in the correct address after convolution)

like a serial-deserializer ?

just to give you an impression, let's do a simple calculation

ok..

assuming that we have 12bit per sensel, this still gives an impressive 800Mhz for each input word

yes...and we must accordingly do the convolution to achieve the maximum expected latency

one is to decimate the data in some meaningfull way, which really depends on the application

and we do not even need to apply the filter on all input words either

can we apply encoding to the data so that we know where the maximum gradient in intensity is present...so that we can apply the filter only at those addresses

if we want to do some kind of image analysis with the help of such a filter, we need to apply it to the input image (which in this case can be heavily decimated) and store the result in memory for further processing

when decimating the image, it may be useful to do a box blur (that is, to average a NxN block, rather than taking one pixel from it)

this improves SNR, and it should be doable with reading each pixel from the input image once (and writing a smaller version of the data for future use, e.g. at next frame)

so the complexity would be O(n) where n is the number of source pixels

definitely

yes..it sounds good

not sure how well that plays with pipelining though, but should probably be doable

(IMHO that will be the main challenge)

also whether it will be zero row or coloumn will depend on the horizontal or vertical axis of the sobel gradient

off for now ... bbl

Hello everyone!

prepend the nick and he will answer as soon as he reads it

@se6astian: My question is if there are any difficulties that I am missing,(something that I don’t see) at implementing T720: The user creates the calibration files and it’s a matter of where to save them. So given the calibration files, at the time of creation, the proposed file structure will be created. If you want to explicitly calibrate the sensor for a set of settings then a new file will be created in a branch of the orig

(I am working on creating the weekly schedule and I need some to see some sub-targets)

we just need to find a system that keeps everything well organized

if different calibrations are required for this parameter change

Hey <BAndiT1983> , I had few doubts , let me know when u r free to answer them

Hi BAandiT1983, I am just checking in to know the status of control daemon though I am following the repo, please reply soon, I will see the logs, thanks in advance.

yes, it's implemented

basically unable to load media .

ThumbnailProvider is the calss which does it for OCBackup currently

hey onenot8!

good night

excellent!

i am interested in designing the arch. of FPGA based sobel filter project

yep, you're not the only one ... there has been quite some interest in this task and the PWM fan controller

great

hey tittynale!

want to know more about the proposal design/outline

lab task ?? don't know anything about it

oh i have gone through that

from our side, there is no specific form for the proposal, what we want to know is how you plan to address the task, what 'milestones' you expect to happen when and what problems you expect and what ideas you have

google itself has some template proposals IIRC, so checking those is probably a good idea

so can i submit more than once

IIRC (but don't quote me on that, double check with GSoC) only the last submission counts

i don't have a new idea

just trying to build a prototype or implement the given paper and then go for further improvements

ok yes ,I'll surely get back to you after generating a minor report or similar

depending on where in the pipeline the filter will be used, the amount of processed data can be huge

convolution would be a minor combinational circuit

that's exactly where I need help

thank you Bertl

of course, parallelization is also a way to speed up things as is decimation of the input data

input data could be floating point ? right ?

(performance and resource reasons actually)

good idea, also some kind of testbench will probably become very useful sooner or later

that is a good question and it probably depends very much on the application

ok, so maybe use build an architecture which can support both the strategies

that is something we have to figure out during the task

(but it is good to mention this and what options there are)

have a good one everyone!

bye bye