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#apertus IRC Channel Logs

2020/11/23

Timezone: UTC


00:44
BAndiT1983
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05:36
Bertl
off to bed now ... have a good one everyone!
05:36
Bertl
changed nick to: Bertl_zZ
06:59
BAndiT1983|away
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08:46
se6ast1an
good day
08:46
se6ast1an
time to continue checking the mixed panel BOM!
08:47
se6ast1an
with the traditional soundtrack of people working on bill off materials
08:47
se6ast1an
BOM-funk MC
08:47
se6ast1an
https://www.youtube.com/watch?v=u5tv9zXgG2Q
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BGeorge42
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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12:50
Bertl_zZ
changed nick to: Bertl
12:50
Bertl
morning folks!
13:06
se6ast1an
good day
15:22
b_george
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16:59
se6ast1an
MEETING TIME!
17:00
se6ast1an
who is here?
17:00
Bertl
is here ...
17:00
BAndiT1983
am also here
17:01
b_george
Hello, I am George, I had sent a message last Friday, to join the team
17:01
se6ast1an
ah, great! hi george!
17:02
Bertl
hell b_george! welcome!
17:02
b_george
Nice to meet you !
17:02
BAndiT1983
Bertl: no time for death metal right now
17:03
se6ast1an
george we read your email with interest
17:03
se6ast1an
did you already have a look at the website/lab to see what might interest you to work on/collaborate?
17:03
Foad95
joined the channel
17:03
se6ast1an
and did you just create a lab account named bgiorgos ?
17:03
se6ast1an
hi foad!
17:03
Foad95
Hello
17:04
Bertl
hello Foad95! welcome too!
17:04
b_george
thank you very much, as you have read, my background is most on hardware design, I saw some project but I didn't figure out what task is occupied from other users or if I can work with collaboration with other members
17:04
Bertl
b_george: +o of course :)
17:05
b_george
Yes, I just created one
17:05
se6ast1an
great, just approved it
17:05
Bertl
b_george: which tasks did you find that interest you?
17:06
b_george
Thank you, dynamic reconfiguration is an interesting task, but I don't know if you have any task in priority
17:07
b_george
You can suggest me one if you believe it has high priority for the project
17:08
Bertl
bluez_[m] plans to work on the dynamic reconfiguration, but there are tons of other hardware related tasks and maybe he is even interested in a collaboration
17:08
Bertl
did you have a look at the Axiom Beta hardware?
17:08
Foad9535
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17:09
anuejn
is here
17:09
Bertl
Foad95: you might want to ditch the web-chat sooner or later and get a 'proper' IRC client
17:09
Foad95
How do I do that?
17:10
b_george
Yes, I had a look
17:10
Bertl
Foad95: there are a number of IRC client available for all platforms, for example Pidgin or if you prefer terminal, irssi
17:11
se6ast1an
there is also hexchat or x-chat
17:11
Bertl
just connect to irc.freenode.net with that an join the #apertus channel
17:11
se6ast1an
Foad95: you can also use the webclient for now, we just see you have connectivity issues
17:11
se6ast1an
but no big deal if it works for you now
17:12
se6ast1an
you can read up on the logs here http://irc.apertus.org/index.php?day=23&month=11&year=2020 in case you get disconnected
17:12
Bertl
b_george: one of the tasks students have tackled several times without 'proper' solution is the FPGA-FPGA interface
17:12
se6ast1an
foad can you also tell us a bit about yourself or what you would be interested to work on in the apertus world?
17:13
Foad95
Yes. I have made films. I also have managed software development projects.
17:13
Bertl
b_george: i.e. the interface between the Zynq and the two routing fabrics (MachXO2) on the main board, because it is trickier than it seems at first glance
17:13
Spirit532
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17:13
Foad95
I also did software product marketing.
17:13
Foad95
I am doing product marketing now for LibreOffice
17:13
Spirit532
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17:14
Bertl
b_george: https://lab.apertus.org/T731 basically
17:15
Bertl
Foad95: nice!
17:15
b_george
Bertl, very good, I can work on it
17:16
b_george
but i need more details of the platforms you use, for example, the connection is through gpio or another port ?
17:16
Foad95
I know Sony F5 and Canon 5D cameras.
17:16
Bertl
b_george: there has been some progress, so you might want to dig into the work students did there, and maybe even contact them for some kind of chat
17:16
Foad95
I own them.
17:17
Bertl
b_george: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/axiom_beta_main_board_v0.36_r1.2.sch.pdf
17:17
se6ast1an
very nice foad, so what could you imagine doing with apertus°?
17:18
Bertl
b_george: the connection is through one (RFW) or two (RFE) LVDS pairs and a single ended clock signal (see page 5 and 6)
17:19
Foad95
I can imagine project management for the next product release.
17:19
b_george
Bertl, as I can read, that is the main pcb of the camera, so you would like to connect two FPGA through this board.
17:19
Foad95
I can imagine working with tech partners (e.g. Magic) to make sure both side are getting what they need.
17:20
Foad95
I can imagine doing outreach to find partners and pilot customers who would be great potential candidates.
17:20
Bertl
b_george: actually three, the main FPGA (Zynq) should be connected with the routing fabrics (MachXO2s) RFW and RFE
17:20
Bertl
b_george: the main purpose of those is to act as reconfigurable GPIO expanders
17:21
Foad95
I can also imagine writing text, content for PR or articles on Medium. I have a few articles online.
17:21
Foad95
about AI
17:21
b_george
I understand
17:21
b_george
Where can I found the student who worked on this task ?
17:22
se6ast1an
https://summerofcode.withgoogle.com/archive/2020/organizations/6145737898852352/
17:23
Bertl
b_george: the last one was apoorva_arora, who mostly worked on the protocol side
17:24
Bertl
https://wiki.apertus.org/index.php/FPGA_based_Bidirectional_Packet_Protocol
17:24
se6ast1an
foad I think any project management or communication related task is challenging to start with as it requires a certain overview/insight of all the things happening in the project but content/outreach I can imagine to work quite well
17:24
se6ast1an
over time you would gain that overview/insight am sure
17:24
se6ast1an
its a very big and complex project
17:24
se6ast1an
even we struggle to stay on top of things happening :)
17:25
Bertl
b_george: https://wiki.apertus.org/index.php/GSoC_Projects (check for Bidirectional Packet Protocol) for the previous students
17:25
Foad95
Content/outreach sounds like a good starting point.
17:26
Foad95
Anyone located in Berlin?
17:26
Bertl
b_george: the task is definitely demanding and obviously easily underestimated
17:27
se6ast1an
Foad95: we go to maker faire berlin every year, so after it will happen again after covid that would be an excellent opportunity to meet in person
17:27
se6ast1an
hopefully next year, but I fear its too soon for covid
17:27
b_george
I agree, however, i have to see the progress of the student in order to work on his protocol, if it is good
17:27
b_george
do you have an overview of his progress ?
17:27
b_george
his/her*
17:28
se6ast1an
every student wrote a report at the end of the program
17:28
se6ast1an
it should be linked to in the overview I think
17:29
se6ast1an
foad I guess we best sit down for a separate meeting soon, should we schedule something over email to discuss the concrete next steps?
17:29
se6ast1an
or do you use any messenger/platform that you prefer?
17:30
Foad95
Yes. Sounds good. Please feel free to write me an email and we can speak over Zoom or Google Hangout.
17:30
b_george
Bertl, I just found hes github, the links on the sited are down
17:30
Foad95
Later this week or any time next week (CET) should be fine.
17:31
b_george
After a brief check, her coding style is good
17:31
se6ast1an
Foad95: great, I will email you in the next couple of days then
17:31
BAndiT1983
b_george: no wonder, Bertl was also the instructor
17:33
b_george
So, I will work on it
17:34
se6ast1an
b_george: I would suggest you dig into the code/report and once you have an overview or a list of questions we can schedule a meeting with the student & mentor here or do it via email if thats easier
17:34
se6ast1an
you can come to IRC anytime of course
17:34
Bertl
b_george: sounds great!
17:34
se6ast1an
there are times when not much is happening but other times when the channel is very active
17:34
Bertl
and yes, hanging around here on IRC is a good idea :)
17:34
se6ast1an
like on mondays when we do the weekly meeting :)
17:35
se6ast1an
with the public logs http://irc.apertus.org/ you can also post a question or comment and check back later if/what someone replied/commented
17:36
se6ast1an
right to continue the meeting lets do reports about last week
17:36
b_george
I totally agree Sebastian! As Bertl was/is the instructor I will send an e-mail to him to arrange a meeting after a full the review of the Task
17:36
se6ast1an
great
17:36
b_george
Is it ok for you Bertl ?
17:36
se6ast1an
BAndiT1983: would you like to start with the report?
17:36
Bertl
b_george: sure, but feel free to contact me here anytime ...
17:37
BAndiT1983
se6ast1an: alright
17:37
b_george
if you are online here all the time better to contact through the chat
17:37
Bertl
both is fine for me
17:38
BAndiT1983
not much from my side, we were mostly working on the PCB scripts to finish the gerber data and to order the PCBs, some fixes were done, as we had just before the finish line some problems with drill holes again, but reading the lib code has shown how the format can be adjusted
17:38
BAndiT1983
resumed also to work on the axiom remote again, not much to report there, but am guiding metal_dent[m] also a bit, so we can resume the development with more speed again
17:38
BAndiT1983
that would be it from me
17:39
Foad95
Sounds good Sebastian!
17:40
se6ast1an
thanks BAndiT1983!
17:40
se6ast1an
anuejn: your turn!
17:40
anuejn
Okay :)
17:41
anuejn
So, besides the things I already reported over the course of the week (mainly axiom micro progress; working hdmi and debayering) I worked on the USB3 plugin
17:41
se6ast1an
you can also give us a brief summary so we do not have to read up the logs from previous days :)
17:42
anuejn
after some (a lot?) of trouble with building quite basic things like debugging facilities and clocking I am now bringing the link between the camera and the plugin module up
17:42
anuejn
currently I am implementing a (software guided) link training with word and bit alingnment
17:43
Bertl
software on the zynq side?
17:44
anuejn
that works up to about 300Mhz ddr on 4 lanes
17:44
anuejn
sadly I wasnt able to get it to work at the targetet 400Mhz ddr
17:44
anuejn
maybe that is si issues?
17:45
anuejn
Bertl: yup software on the zynq side
17:45
anuejn
that then controls registers inside the machxo2 via jtag
17:46
anuejn
I have build some more or less fancy way to describe hardware and software from the same codebase
17:47
anuejn
https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/plugin_module_streamer/rx.py#L109
17:47
anuejn
most of that code is using nmigen and builds hdl
17:48
Foad95
left the channel
17:48
Bertl
did the 400MHz DDR link work but with bad quality or not at all?
17:48
anuejn
but the method annotated with @driver_method is bundeled with some code and runs on the zynq
17:49
anuejn
Bertl: I cant really say because my current bit alignment method requires that you can see the training pattern at at least one tap for 0.1 Second without error
17:50
Bertl
and was it done on all four links at the same time or did you (also?) test each lane separately?
17:51
anuejn
I first do word alignment by only looking at the data received by lane 0 and then do bit alignemnt for each lane individually
17:51
anuejn
word alignment can only be done for all lanes together (that is dictated by the fpga architecture)
17:52
Bertl
interesting order
17:52
anuejn
yup, thats what I thought
17:52
Bertl
anyway, so the bit alignment failed on one or all lanes?
17:52
anuejn
on all lanes
17:53
Bertl
so probably mor a systemic problem than a 'bad' connection or 'unfortunate' routing
17:53
Bertl
*more
17:54
Bertl
termination was configured properly? :)
17:55
anuejn
the problem with doing bit alignment first is that one has to be rather smart about not picking taps for lanes that result in problems during word alignemt which cant be done individually
17:55
anuejn
all lanes are internally terminated with 100 Ohms
17:56
anuejn
thats it from my side I guess :)
17:56
Bertl
thanks a bunch!
17:56
anuejn
but I am quite happy to discuss my problem with you after the meeting Bertl
17:56
Bertl
sure, anytime
17:57
se6ast1an
many thanks anuejn!
17:57
se6ast1an
quick updates from me
17:57
se6ast1an
then Bertl will finished us off as usual!
17:57
se6ast1an
I met with manfred last week and he handed me samples of attempts to cnc mill the rubber sheets for the axiom beta compact enclosure feet.
17:57
se6ast1an
unfortunately it did not work very well:
17:58
se6ast1an
https://cloud.apertus.org/index.php/apps/gallery/s/eyDpYSZDNs3yKZc
17:58
se6ast1an
a few days later he tried the drag knife approach and that produced very good results, also pictures in the gallery above. See the file names for description of the images.
17:58
se6ast1an
Max finished the first release candidate video for the next Team Talk episode TT15.5.
17:58
se6ast1an
I reviewed it today and provided some more insert footage/material. The SATA plugin module progress is tricky as Florents recent progress needs to be incorporated but that requires new voice overs or text inserts, left the decision how to ingreate it to Max. Shouldn't be long before I get a new version that is probably close to a final release already. Draft for internal review will be shared enxt. Then we will create an article around it and release.
17:59
se6ast1an
OSHPark order for 9 mixed panels has been placed and JLCPCB order is just pending payment, waiting for Oscar here.
17:59
se6ast1an
Tele promised to have the SMT/THT assembly offer for us ready today, will contact them tomorrow as we have not received anything.
17:59
se6ast1an
Bill of Material (BOM) review for the mixed panel run is pretty far but still work in progress and pending some feedback from Tele currently, but we should be ready to order the missing components pretty soon and I need to count/measure the reels we already have in the office.
17:59
se6ast1an
I also adjusted the PCB holding clamps design in the AXIOM Beta compact enclosure today to account for the maximum possible tolerances of the CMV12000, pins and andon sockets.
17:59
se6ast1an
will try to call oscar after the meeting
17:59
se6ast1an
thats it from my side
17:59
se6ast1an
Bertl: the stage is yours!
17:59
Bertl
great! thanks!
18:01
Bertl
I spent some quality time on going through endless part lists with sebastian (we had a bunch of chat sessions for that)
18:01
Bertl
and on last minute PCB revisions to get everything ready for the panels
18:02
Bertl
aside from that, I did work on the three current projects which require some hardware testing and firmware/gateware to allow that
18:03
Bertl
first the 'new' power board where we need firmware to control the newly added switchers
18:03
Bertl
then I completed the SATA plugin board so we can recreate the setup _florent_ has been using
18:04
Bertl
and finally I finished reworking the digitizer so that at least in theory now everything there should be working ... will hopefully get to test that this week too
18:04
Bertl
there were a bunch of hardware issues (errors in the schematic/pcb which went unnoticed when we ordered the PCB)
18:05
Bertl
so some rework was required ... here are the most interesting rework hacks just for fun:
18:05
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/digitizer_rework.jpg
18:05
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/digitizer_rework2.jpg
18:06
Bertl
that's it from my side for this week.
18:08
se6ast1an
many thanks!
18:08
se6ast1an
I ordered 4 sata ssds a few days ago that should be able to do 400MB/s sustainable write
18:08
se6ast1an
for Bertl to test with
18:09
se6ast1an
currently florents fpga code is Gen 2 only so limited to 300MB/s
18:09
se6ast1an
but he said he wants to look into that as well
18:09
se6ast1an
anyone else with comments/reports/questions/etc.?
18:11
se6ast1an
many thanks everyone! MEETING CONCLUDED!
18:12
Bertl
thanks for the moderation!
18:12
b_george
Thank you very much
18:12
b_george
Have a nice evening
18:13
se6ast1an
my pleasure!
18:13
se6ast1an
you too b_george
18:16
anuejn
Bertl: do you have any idea for what I could try?
18:16
anuejn
or shall I explain my setup a bit more?
18:16
Bertl
I wouldn't mind getting a more detailed explanation
18:16
anuejn
Okay
18:17
Bertl
but in general what might be interesting to try is to test with small frequency steps
18:17
anuejn
so currently I have test gateware loaded into the zynq which outputs the testpattern 0b00000110 on all lanes repeatedly
18:17
Bertl
i.e. not 300MHz then 400Mhz, try with 333, 350, 380, etc
18:18
anuejn
Bertl: that i a bit hard to do because untill now i was just changing the fclk frequency
18:18
anuejn
I have a counter in the machxo that counts the words that are not equal to that testpattern for each lane
18:19
anuejn
and for each lane I can set the delay and I can bitslip all lanes together
18:20
anuejn
my current training algorithm sets the delay of all lanes to tap 15 (out of 32 taps) and then does bitslips untill it finds the testpattern once
18:21
Bertl
anuejn: the FCLK is easy to adjust, no?
18:21
anuejn
https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/plugin_module_streamer/rx.py#L64
18:22
anuejn
then for each lane I go through all taps and measure the number of words that are not equals the testpattern in a given time (https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/plugin_module_streamer/rx.py#L152)
18:22
anuejn
Bertl: yup but has quite limited resolution
18:23
Bertl
you are not feeding a 300MHz FCLK directly to the MachXO2 or do you?
18:23
Bertl
if so, that might as well explain the issues
18:23
anuejn
I am driving the word domain from the fclk and use a pll to get to generate the bitclk
18:23
anuejn
I transmit the word clock (100Mhz) to the MachXO
18:24
Bertl
please elaborate on the clock setup
18:24
Bertl
PS (FCLK) -> ?
18:25
anuejn
PS -> PLL -> OSERDES
18:25
anuejn
PS -> MACHXO -> PLL -> ISERDES
18:25
Bertl
PS -> MACHXO (how?)
18:26
anuejn
on the zynq side directly from the clock signal into the io buffer
18:26
anuejn
on the machxo side from a clock capable input into the pll
18:26
Bertl
over LVDS?
18:26
anuejn
yup
18:27
Bertl
please use an OSERDES for the clock as well
18:27
anuejn
ah okay, whats the consideration here?
18:28
Bertl
when you have a clock which is 'related' to data, you want, if possible, to have the same path
18:28
Bertl
this affects jitter and phase alignment as well as noise in general
18:29
Bertl
so, DDR data, e.g. with ODDR, use ODDR for the clock as well
18:29
Bertl
data via OSERDES, use an OSERDES for the clock too
18:29
Bertl
of course, based on the same PLL/clock as the others
18:30
anuejn
okay, will try
18:30
anuejn
builds a fresh zynq bitstream
18:31
Bertl
for the FCLK and small steps part
18:32
Bertl
use a rather low frequency for FCLK and a high multiplier for the PLL
18:32
Bertl
this way you have more options on the clock frequencies
18:35
anuejn
okay
19:05
b_george
left the channel
21:05
anuejn
so after some experimentation I cant go much further than 316Mhz
21:06
anuejn
changing the clock to be output via oserdes also doesnt change much
21:07
Bertl
very interesting
21:08
Bertl
given that we can do 700+ MHz on the zynq side
21:08
anuejn
yup
21:09
anuejn
and that 400Mhz should be in spec
21:09
Bertl
yes, on both side
21:09
Bertl
*sides
21:10
vup
hmm considering hdmi is working at much higher speeds, I would think the routing shouldn't be a problem aswell
21:10
Bertl
yep
21:11
Bertl
are you testing on the beta or micro?
21:14
anuejn
on the micro
21:17
anuejn
hm... now that i reread the datasheet it seems that the spec states 756Mbps / 378Mhz as the maximum
21:18
anuejn
which is still a good 50Mhz away from what I am getting but it is getting close
21:19
Bertl
nevertheless, might be worth trying on the beta, just to see if the results are consistent
21:20
anuejn
hm... I need jtag via openocd for my design to work
21:20
anuejn
so that might be quite hard atm
21:20
Bertl
why?
21:21
Bertl
I mean, why might that be quite hard?
21:21
anuejn
Is the openocd fork of bluez_[m] in a usable state?
21:21
Bertl
should be fine, yes
21:21
anuejn
ah nice :)
21:22
Bertl
all you need is the pass through for the RF
21:22
anuejn
can you guide me through the things I have to do?
21:23
Bertl
well, you need the kernel driver
21:23
Bertl
(including overlays)
21:24
Bertl
for now, still some scripts to initialize GPIOs
21:24
Bertl
(this hopefully will be addressed soon)
21:24
Bertl
https://github.com/Swaraj1998/axiom-beta-rfdev
21:25
Bertl
you also need to make sure your PIC code is recent enough to allow the pass through
21:25
Bertl
(but that's easy to check and also easy to update if not)
21:28
anuejn
shit I broke my beta power cord :(
21:30
anuejn
ah nice I have found another one :)
21:31
anuejn
half assembled usb-c cables are not the most rigid object in existence ;)
21:33
comradekingu
left the channel
21:41
comradekingu
joined the channel
21:51
anuejn
bluez_[m]: that is actually really nice documented :)
21:51
anuejn
props to you
23:12
BAndiT1983
changed nick to: BAndiT1983|away
23:47
anuejn
Bertl: I loaded the kernel module but got this: https://paste.niemo.de/qapumafoga.yaml
23:47
anuejn
is that a sign that I need to update something?
23:53
Bertl
did you run the scripts as instructed by the how-to?
23:54
anuejn
yup
23:55
Bertl
does the PIC show up fine in i2cdetect?
23:56
anuejn
on which bus?
23:56
Bertl
2
23:56
anuejn
nope
23:57
anuejn
maybe it is time to restart the camera
23:59
mumptai
joined the channel