#apertus IRC Channel Logs

good day

with the traditional soundtrack of people working on bill off materials

https://www.youtube.com/watch?v=u5tv9zXgG2Q

morning folks!

MEETING TIME!

Hello, I am George, I had sent a message last Friday, to join the team

hell b_george! welcome!

Bertl: no time for death metal right now

did you already have a look at the website/lab to see what might interest you to work on/collaborate?

and did you just create a lab account named bgiorgos ?

Hello

thank you very much, as you have read, my background is most on hardware design, I saw some project but I didn't figure out what task is occupied from other users or if I can work with collaboration with other members

Yes, I just created one

b_george: which tasks did you find that interest you?

You can suggest me one if you believe it has high priority for the project

did you have a look at the Axiom Beta hardware?

Foad95: you might want to ditch the web-chat sooner or later and get a 'proper' IRC client

Yes, I had a look

there is also hexchat or x-chat

Foad95: you can also use the webclient for now, we just see you have connectivity issues

you can read up on the logs here http://irc.apertus.org/index.php?day=23&month=11&year=2020 in case you get disconnected

foad can you also tell us a bit about yourself or what you would be interested to work on in the apertus world?

b_george: i.e. the interface between the Zynq and the two routing fabrics (MachXO2) on the main board, because it is trickier than it seems at first glance

I also did software product marketing.

Foad95: nice!

but i need more details of the platforms you use, for example, the connection is through gpio or another port ?

b_george: there has been some progress, so you might want to dig into the work students did there, and maybe even contact them for some kind of chat

b_george: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/axiom_beta_main_board_v0.36_r1.2.sch.pdf

b_george: the connection is through one (RFW) or two (RFE) LVDS pairs and a single ended clock signal (see page 5 and 6)

Bertl, as I can read, that is the main pcb of the camera, so you would like to connect two FPGA through this board.

I can imagine doing outreach to find partners and pilot customers who would be great potential candidates.

b_george: the main purpose of those is to act as reconfigurable GPIO expanders

about AI

Where can I found the student who worked on this task ?

b_george: the last one was apoorva_arora, who mostly worked on the protocol side

foad I think any project management or communication related task is challenging to start with as it requires a certain overview/insight of all the things happening in the project but content/outreach I can imagine to work quite well

its a very big and complex project

b_george: https://wiki.apertus.org/index.php/GSoC_Projects (check for Bidirectional Packet Protocol) for the previous students

Anyone located in Berlin?

Foad95: we go to maker faire berlin every year, so after it will happen again after covid that would be an excellent opportunity to meet in person

I agree, however, i have to see the progress of the student in order to work on his protocol, if it is good

his/her*

it should be linked to in the overview I think

or do you use any messenger/platform that you prefer?

Bertl, I just found hes github, the links on the sited are down

After a brief check, her coding style is good

b_george: no wonder, Bertl was also the instructor

b_george: I would suggest you dig into the code/report and once you have an overview or a list of questions we can schedule a meeting with the student & mentor here or do it via email if thats easier

b_george: sounds great!

and yes, hanging around here on IRC is a good idea :)

with the public logs http://irc.apertus.org/ you can also post a question or comment and check back later if/what someone replied/commented

I totally agree Sebastian! As Bertl was/is the instructor I will send an e-mail to him to arrange a meeting after a full the review of the Task

Is it ok for you Bertl ?

b_george: sure, but feel free to contact me here anytime ...

if you are online here all the time better to contact through the chat

not much from my side, we were mostly working on the PCB scripts to finish the gerber data and to order the PCBs, some fixes were done, as we had just before the finish line some problems with drill holes again, but reading the lib code has shown how the format can be adjusted

that would be it from me

thanks BAndiT1983!

Okay :)

you can also give us a brief summary so we do not have to read up the logs from previous days :)

currently I am implementing a (software guided) link training with word and bit alingnment

that works up to about 300Mhz ddr on 4 lanes

maybe that is si issues?

that then controls registers inside the machxo2 via jtag

https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/plugin_module_streamer/rx.py#L109

but the method annotated with @driver_method is bundeled with some code and runs on the zynq

and was it done on all four links at the same time or did you (also?) test each lane separately?

word alignment can only be done for all lanes together (that is dictated by the fpga architecture)

yup, thats what I thought

on all lanes

*more

the problem with doing bit alignment first is that one has to be rather smart about not picking taps for lanes that result in problems during word alignemt which cant be done individually

thats it from my side I guess :)

but I am quite happy to discuss my problem with you after the meeting Bertl

many thanks anuejn!

then Bertl will finished us off as usual!

unfortunately it did not work very well:

a few days later he tried the drag knife approach and that produced very good results, also pictures in the gallery above. See the file names for description of the images.

I reviewed it today and provided some more insert footage/material. The SATA plugin module progress is tricky as Florents recent progress needs to be incorporated but that requires new voice overs or text inserts, left the decision how to ingreate it to Max. Shouldn't be long before I get a new version that is probably close to a final release already. Draft for internal review will be shared enxt. Then we will create an article around it and release.

Tele promised to have the SMT/THT assembly offer for us ready today, will contact them tomorrow as we have not received anything.

I also adjusted the PCB holding clamps design in the AXIOM Beta compact enclosure today to account for the maximum possible tolerances of the CMV12000, pins and andon sockets.

thats it from my side

great! thanks!

and on last minute PCB revisions to get everything ready for the panels

first the 'new' power board where we need firmware to control the newly added switchers

and finally I finished reworking the digitizer so that at least in theory now everything there should be working ... will hopefully get to test that this week too

so some rework was required ... here are the most interesting rework hacks just for fun:

http://vserver.13thfloor.at/Stuff/AXIOM/digitizer_rework2.jpg

many thanks!

for Bertl to test with

but he said he wants to look into that as well

many thanks everyone! MEETING CONCLUDED!

Thank you very much

my pleasure!

Bertl: do you have any idea for what I could try?

I wouldn't mind getting a more detailed explanation

but in general what might be interesting to try is to test with small frequency steps

i.e. not 300MHz then 400Mhz, try with 333, 350, 380, etc

I have a counter in the machxo that counts the words that are not equal to that testpattern for each lane

my current training algorithm sets the delay of all lanes to tap 15 (out of 32 taps) and then does bitslips untill it finds the testpattern once

https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/plugin_module_streamer/rx.py#L64

Bertl: yup but has quite limited resolution

if so, that might as well explain the issues

I transmit the word clock (100Mhz) to the MachXO

PS (FCLK) -> ?

PS -> MACHXO -> PLL -> ISERDES

on the zynq side directly from the clock signal into the io buffer

over LVDS?

please use an OSERDES for the clock as well

when you have a clock which is 'related' to data, you want, if possible, to have the same path

so, DDR data, e.g. with ODDR, use ODDR for the clock as well

of course, based on the same PLL/clock as the others

use a rather low frequency for FCLK and a high multiplier for the PLL

okay

so after some experimentation I cant go much further than 316Mhz

very interesting

yup

yes, on both side

hmm considering hdmi is working at much higher speeds, I would think the routing shouldn't be a problem aswell

are you testing on the beta or micro?

hm... now that i reread the datasheet it seems that the spec states 756Mbps / 378Mhz as the maximum

nevertheless, might be worth trying on the beta, just to see if the results are consistent

so that might be quite hard atm

I mean, why might that be quite hard?

should be fine, yes

all you need is the pass through for the RF

well, you need the kernel driver

for now, still some scripts to initialize GPIOs

https://github.com/Swaraj1998/axiom-beta-rfdev

(but that's easy to check and also easy to update if not)

ah nice I have found another one :)

bluez_[m]: that is actually really nice documented :)

is that a sign that I need to update something?

yup

on which bus?

nope