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#apertus IRC Channel Logs

2019/06/23

Timezone: UTC


02:06
illwieckz
left the channel
02:07
RexOrCine
changed nick to: RexOrCine|away
06:34
Bertl_oO
off to bed now ... have a good one everyone!
06:34
Bertl_oO
changed nick to: Bertl_zZ
09:23
BAndiT1983|away
changed nick to: BAndiT1983
09:41
se6astian|away
changed nick to: se6astian
09:48
se6astian
good day
11:39
se6astian
changed nick to: se6astian|away
11:40
se6astian|away
changed nick to: se6astian
12:03
Y_G
joined the channel
12:20
Y_G
Hi se6astian, I had some questions about the setting the analog gain (PGA).
12:20
Y_G
In the `set_gain.sh`, along with setting the analog gain(reg 115), the register for ADC_range(116), Adc_range_mult2(reg 100) and offset(reg 87 and 88) are also being set.
12:20
Y_G
In daemon implementation do we want something like `set analog_gain` to do all these things or just set the register for analog gain (115).
12:35
BAndiT1983
changed nick to: BAndiT1983|away
12:35
BAndiT1983|away
changed nick to: BAndiT1983
12:52
BAndiT1983
hi Y_G, if i remember correctly then the script was meant like a preset first and values selected fitting it
12:52
se6astian
`set analog_gain` to do all these things <- that
12:54
BAndiT1983
// Set division first, to prevent overwriting gain values
12:54
BAndiT1983
SetConfigRegister(115, _divPGA[_analogGainValue]);
12:54
BAndiT1983
SetConfigRegister(115, _gainPGA[_analogGainValue]);
12:54
BAndiT1983
// SetConfigRegister(100, 1);
12:54
BAndiT1983
// SetConfigRegister(87, 2000);
12:54
BAndiT1983
// SetConfigRegister(88, 2000);
12:54
BAndiT1983
this was in previous version of CMV12000Adapter, now CMV12000Module
12:54
BAndiT1983
diff -> https://github.com/apertus-open-source-cinema/axiom-control-daemon/commit/4ea5116cefc38b418e565d118f57422feca599e9#diff-96249d75c14233a0fdad079c414dc755
12:58
BAndiT1983
there are 2 ways to solve it, add the lines again, which were removed from analog_gain or test set_register and re-create the script with it
13:03
aombk
left the channel
13:06
Y_G
I think adding the lines back should be sufficient
13:08
aombk
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13:14
BAndiT1983
then the infos i had back then were different, from what it's now
13:14
se6astian
sounds good
13:14
BAndiT1983
so, off for a moment, will be back a bit later
13:15
BAndiT1983
changed nick to: BAndiT1983|away
13:25
Y_G
left the channel
13:47
illwieckz
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13:53
Y_G
joined the channel
13:53
Y_G
left the channel
14:08
Bertl_zZ
changed nick to: Bertl
14:08
Bertl
morning folks!
14:08
apurvanandan[m]
Good morning
14:11
apurvanandan[m]
Do the SERDES primitives adjust the clock in source synchronous systems to the middle of the eye?
14:11
apurvanandan[m]
Like the ISERDES
14:18
Bertl
no, you need to do any adjustments with timing constraints or actively with delay elements
14:20
apurvanandan[m]
Ok, great info :)
14:25
Bertl
typically you want to use the same I/O element to generate the clock
14:26
Bertl
so for example, if you use a DDR I/O element for your data, you also use one to generate the clock
14:27
Bertl
if you utilize an OSERDES for the data, you also want to use an identically configured OSERDES for the clock signal
14:27
Bertl
this ensures that all the timing and phase relations are identical
14:27
apurvanandan[m]
ahh, I see
14:30
apurvanandan[m]
For the data, I used two OSERDES, a master with a slave SERDES. So, do I need to use two SERDES again for the clock?
14:32
Bertl
that would be the 'smart' thing to do :)
14:33
apurvanandan[m]
Okay :)
14:47
illwieckz
left the channel
14:51
illwieckz
joined the channel
15:03
aSobhy|away
changed nick to: aSobhy
15:51
Bertl
hey aSobhy! How's it going?
16:07
illwieckz_
joined the channel
16:09
illwieckz
left the channel
16:34
aSobhy
I'm very delayed :/
16:34
aSobhy
I'm stuck-ed at receiver side at the deserializer module,
16:34
aSobhy
I left that part and simulating the rest
16:34
aSobhy
(write a small cpp file to get the seed with longest words that will lead me to a non reset "00000000" before looping again)
16:34
aSobhy
I almost finished simulation and I'll be back to the deserializer and start docummentation
16:36
Bertl
hmm, are you talking about the PRNG here?
16:38
aSobhy
yeah the cpp for PRNG
16:40
Bertl
well, there are well known polynomials with length 2^n-1
16:42
Bertl
https://www.maximintegrated.com/en/app-notes/index.mvp/id/4400
16:42
Bertl
for example lists them
16:43
Bertl
https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Some_polynomials_for_maximal_LFSRs
16:44
Bertl
so for those you always know that they will produce 2^n-1 values before returning and thus reach each and every state except for '0' or '~0' depending on the type of LFSR
16:45
aSobhy
I used 8-bit shift with bits 5.3.2.0 with seed "11100111 and found a 254 word generated before reaching the reset state "00000000"
16:48
aSobhy
254 out of 256 possible words
16:48
Bertl
okay, but why do you want that?
16:49
Bertl
if you look at the list (I posted) you see that the polynom 6.5.4.0 for 8bit will give you 255 values
16:51
aSobhy
It has no purpose that's what I thought
17:02
aSobhy
okay I changed it it gives 255 with no zeros :)
18:22
illwieckz_
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18:35
illwieckz_
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19:19
BAndiT1983|away
changed nick to: BAndiT1983
20:04
niemand
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20:07
aombk
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20:07
aombk
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20:29
Y_G
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20:30
aombk2
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20:31
BAndiT1983
changed nick to: BAndiT1983|away
20:32
aombk
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21:10
niemand
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22:09
se6astian
off to bed
22:09
se6astian
good night
22:09
se6astian
changed nick to: se6astian|away
22:20
illwieckz_
changed nick to: illwieckz
22:35
Y_G
left the channel
22:47
Bertl
off for now ... bbl
22:47
Bertl
changed nick to: Bertl_oO