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#apertus IRC Channel Logs

2019/03/23

Timezone: UTC


23:51
RexOrCine
changed nick to: RexOrCine|away
00:00
vup2
Bertl_oO: do you know by chance wether the axihp ports of the zynq support write interleaving?
00:01
vup2
also looking at axihp_writer.vhd is there any reason to not start write data transactions indepentent of the address transactions?
00:02
vup2
in this line https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/peripherals/soc_main/axihp_writer.vhd#L142
00:02
Bertl_oO
what do you mean by 'write interleaving'?
00:03
vup2
Bertl_oO: issuing multiple addresses with different AXI ID's
00:04
vup2
and then transfering the data for those burst's interleaved
00:04
vup2
so lets say you have got awid 0 and 1 and then do one beat for awid 0 and then one for 1 and so on
00:05
vup2
(obviously for the write transactions you would have to set wid to the corresponding awid)
00:05
Bertl_oO
you can do that but there is no real advantage in doing so I guess
00:05
vup2
i guess it could improve a interconnect a bit
00:06
Bertl_oO
and data and addresses should be fairly independent (even in the quite old writer)
00:06
vup2
well looking at the line linked above, could active not be replaced by enabled?
00:06
Bertl_oO
the active signal is just to empty out the fifos
00:07
Bertl_oO
when you want to reload the FPGA config, you need to make sure that there are no outstanding transactions
00:07
Bertl_oO
because the AXI bus doesn't get reset and you cannot reset it either
00:08
Bertl_oO
(except for a reboot)
00:09
Bertl_oO
so a mechanism is required to stop feeding new addresses and wait till all current transactions have finished
00:10
Bertl_oO
for the interleaving part, the limiting factor is typically the bandwidth on the AXI master, so not sure what interleaved transactions would help
00:12
Bertl_oO
but feel free to experiment and try different scenarios
00:12
vup2
yeah thinking a bit more about it, it probably wouldn't do much
00:12
Bertl_oO
with recent Vivado you also have some AXI checker and even a BFM to test with
00:13
Bertl_oO
something I really missed back then :)
00:13
vup2
re the active stuff: i don't quite understand how the line i linked ties in with the emptying the outstanding transactions
00:14
vup2
yeah the axi checker seems quite nice
00:14
Bertl_oO
there is a maximum number of outstanding transactions
00:14
Bertl_oO
the current in-flight transactions are counted in 'active'
00:14
vup2
yes
00:14
Bertl_oO
i.e. addresses submitted for a data transaction
00:15
Bertl_oO
once there are no addresses submitted, the data submission stops
00:15
Bertl_oO
this allows to align address and data when shutting down the writers
00:16
vup2
ahh ok
00:16
Bertl_oO
it might not be the most elegant solution, but it certainly worked :)
00:17
vup2
i was thinking of it after the reload and then trying to clean up the fifo
00:18
Bertl_oO
after reload you already lost
00:18
Bertl_oO
because there is an 'unknown' number of partial transactions in the AXI buffers
00:18
vup2
well you could read the fifo level
00:19
Bertl_oO
how?
00:19
vup2
SAXIHP{0-3}RCOUNT[7:0]
00:19
vup2
s/RCOUNT/WCOUNT/
00:19
vup2
and also SAXIHP{0-3}WACOUNT[5:0]
00:20
vup2
(these come out of the ps7 block)
00:20
Bertl_oO
hmm, might work
00:20
Bertl_oO
of course you might need to feed controlled amounts of dummy data
00:21
Bertl_oO
or somehow terminate the transactions (which I do not know if it is possible)
00:21
Bertl_oO
but definitely worth investigating
00:21
Bertl_oO
what are your plans on the AXI (writer/reader) side?
00:22
Bertl_oO
are you 'just' toying around a little to get comfortable or do you have some plans/ideas how to improve/adapt this code already?
00:22
vup2
well if DATA is missing you could just issue some addresses, these could even point to somewhere non existant, because as far as i can tell it should still complete the transaction
00:23
vup2
and if addresses are missing you just issue some burst to clean that out
00:23
vup2
anuejn and me have been thinking of rewriting the gateware in nmigen
00:23
vup2
so i just started by reading the axi spec and looking at your implementations
00:23
Bertl_oO
ah, so that is preparations for a migen AXI gateway
00:24
vup2
yeah
00:24
Bertl_oO
or probably more a bridge
00:25
vup2
yes, we are not quite sure how we want to do AXI
00:25
vup2
for things like configurations stuff a high level api would be quite nice where you just say these are configuration registers, map them to these addresses
00:25
Bertl_oO
what I haven't figured out yet is what the best clock rate for driving the masters would be
00:26
vup2
well looking at SAXIHP{0-3}WCOUNT[7:0] would probably yield a interesting datapoint for benchmarking them
00:26
Bertl_oO
there is a certain minimum clock you want to achieve to get the throughput, but I'm not sure how well this is actually decoupled from the bus and backpone
00:26
Bertl_oO
*backbone
00:26
vup2
as you would want them to be always filled
00:26
Bertl_oO
yes, that is a good idea
00:27
Bertl_oO
I'd also appreciate a solution to the 'priority' issue we are still seeing under extreme load (i.e. CPU stealing memory cycles from the FPGA)
00:28
vup2
oh yeah, had the same problem the other way around
00:28
Bertl_oO
from the configuration I believe we have top priority on read and write from the fabric, but still, running memory intensive I/O hurts
00:28
vup2
using the ACP port completely starves the cpu
00:29
Bertl_oO
so either we are missing something in the configuration or the Zynq AMBA is slightly borked
00:29
vup2
how are you setting the priority atm?
00:30
Bertl_oO
both on the FPGA side (via BUS) and on the CPU side via registers
00:31
Bertl_oO
IIRC, the bus side is kind of ignored (not implemented) on the Zynq
00:32
vup2
the QOS values?
00:32
Bertl_oO
but that's handwaving, I'd have to check the stuff we tried back then
00:37
vup2
ok i will keep that in mind, when we are testing axi things, maybe we can figure something out
00:37
Bertl_oO
that'd be really great! :)
00:42
vup2
ok heading to bed, good night!
00:44
aSobhy
hello Bertl :)
00:45
Bertl_oO
hey aSobhy!
00:45
aSobhy
I have speed up my code some more i reached 257 mhz on maxv
00:45
Bertl_oO
simulation or real?
00:45
aSobhy
real
00:46
Bertl_oO
not bad, how did you verify that it works?
00:48
aSobhy
I meant by real that I have run my code on "Quartus Prime Lite Edition " on maxv fpga
00:48
aSobhy
not on a real fpga
00:48
Bertl_oO
ah, so simulation (at best)
00:49
Bertl_oO
post implementation simulation I hope?
00:49
aSobhy
sorry for that :)
00:51
aSobhy
are you mean the simulation do file or what ?
00:51
aSobhy
do you *
00:52
Bertl_oO
I mean, what kind of simulation did you run
00:53
aSobhy
modelSim
00:54
Bertl_oO
yeah, but after synthesis (functional simulaton) or after placement and routing (i.e. timing based simulation)
00:56
aSobhy
yeah ok after placement and routing :)
00:57
Bertl_oO
well, so only 43 MHz to go then :)
00:58
Bertl_oO
is the code up-to-date and easy on the eyes?
00:58
aSobhy
as in Quatus is doing a sequential tasks including synthesis and routing
01:00
Bertl_oO
nah, doesn't look like the github repo is up-to-date
01:00
aSobhy
just one miniute
01:00
futarisIRCcloud
left the channel
01:00
aSobhy
minute *
01:00
aSobhy
iam pushing the code right now :)
01:02
aSobhy
now it is :)
01:03
aSobhy
I distributed the long input logic gates to be in a pipeline form as the max input to any logic gate is 2 inputs
01:03
Bertl_oO
still not properly formatted though ... note that this will be a critical aspect in the proporsal evaluation
01:04
aSobhy
and the worst paths are in those gates
01:04
Bertl_oO
you might consider sampling on both clock edges
01:05
aSobhy
is that the max words in one line ? or something else ?
01:06
Bertl_oO
nah, the long lines are just the tip of the iceberg
01:07
aSobhy
but when i sample on both edges the speed drooped to half
01:07
Bertl_oO
ser2par.vhd, first problem in line 5 and second in line 10
01:07
aSobhy
GENERIC and the space :/
01:08
Bertl_oO
when you sample on both edges, you move twice the amount of data
01:08
Bertl_oO
so if you manage to get to 150MHz, you are already processing 300MHz worth of data
01:08
aman__
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01:09
Bertl_oO
so, what's wrong in line 38?
01:09
aSobhy
mmmm okay
01:10
aSobhy
yes missing a space
01:10
Bertl_oO
and in line 80?
01:10
aman_
left the channel
01:11
aSobhy
missing spaces
01:11
Bertl_oO
actually there is the missing space :)
01:11
Bertl_oO
you normally do not put a space before the colon (',')
01:11
Bertl_oO
lines 100-105?
01:14
aSobhy
so is the right to put a space after and before or what ?
01:14
Bertl_oO
separators like ';' or ',' only get a space after them
01:14
aSobhy
missing space before the "=>"
01:15
Bertl_oO
oeprators get spaces around the operators
01:15
aSobhy
ok :)
01:15
Bertl_oO
one acceptable exception to that is arithmetic stuff like SIZE-1
01:15
Bertl_oO
which you can format either way as long as you do it consistently
01:16
Bertl_oO
so what's wrong in lines 90-156?
01:17
aSobhy
the blank lines ?
01:17
Bertl_oO
yeah, that and something else, which is also a problem in lines 19-88 :)
01:18
aSobhy
i have a miss understand : how i write the generic what capitalize should done ?
01:18
Bertl_oO
indentation is missing there
01:18
Bertl_oO
you have a block generated by the architecture - begin - end architecture;
01:19
Bertl_oO
the parts inside are, well, 'inside' so should have one level of indentation
01:20
Bertl_oO
for the genrics, they are like constants for the code in question, so you normally format them all upper case (same for constants)
01:20
Bertl_oO
but I'm not even considering those details at the moment
01:21
aSobhy
so in my code in line 5 parallel_size should be PARALLEL_SIZE
01:22
Bertl_oO
yep, and personally I'd put the generic in a single line
01:22
Bertl_oO
same indentation as the clk in line 8
01:22
Bertl_oO
s/single/separate/
01:23
aSobhy
as in line 33 but missing the capitalization ?
01:23
Bertl_oO
yep
01:24
Bertl_oO
note that with VHDL 2008 you can drop all the component stuff for your code and use entity instantiation (avoids writing the same thing twice)
01:25
Bertl_oO
but that's okay was just for your information
01:25
aSobhy
actually at the beginning I opened the github of apertus and didint catch those difference but no one can learn from the first time :)
01:26
Bertl_oO
well, that's why I'm pointing out all the problems now and not after your submission :)
01:27
aSobhy
OK, I appreciate that :D thanks alot :D
01:28
Bertl_oO
you're welcome!
01:28
Bertl_oO
line 148?
01:28
aSobhy
missing a space
01:28
Bertl_oO
bingo!
01:29
aSobhy
bingo :)
01:30
aSobhy
so the next mission is to sample on the both edges
01:30
Bertl_oO
yes, try that as well as wrapping everything into a commandline build and test suite setup
01:31
Bertl_oO
i.e. something which can be build with a single script/make without using a GUI and verify that everything works as intended
01:32
aSobhy
a do file or a testbench
01:32
aSobhy
or something else
01:32
Bertl_oO
whatever works is fine
01:33
Bertl_oO
or more precisely, whatever works without the need to click somewhere around is fine ;)
01:33
aSobhy
yeah those GUIs are killing me and Iam working with command lines
01:34
Bertl_oO
that is a common problem and why all serious stuff is command-line based anyway
01:54
apurvanandan[m]
I have a doubt, In the task it is written that we can assume input clock of 100MHz but we have to receive data at both edges of 300 MHz clock.
01:54
apurvanandan[m]
From where will we get this 300 MHz
02:04
Bertl_oO
that is a good observation, but the task also says that you can use 'magic stuff' the FPGA manufacturers provide (for free) like DDR or in this case PLL/MMCM
02:06
Bertl_oO
so for the 100 -> 300 (or whatever you need) step you want to use some kind of PLL ... but I'm also fine if you add your own external clock (as long as it is reasonable :)
02:10
apurvanandan[m]
Actually I am trying to avoid any manufacturer's stuff.
02:10
apurvanandan[m]
So I think I will use 300 MHz in place of 100 MHz
02:11
Bertl_oO
so be it
02:12
apurvanandan[m]
Is there any proposal template that we can follow or better if a example proposal
02:13
Bertl_oO
not from our side, but IIRC, GSoC always hase some 'basic' templates
02:13
Bertl_oO
but let me double check, we probably did something last year
02:15
Bertl_oO
https://wiki.apertus.org/index.php/GSoC_Overview
02:15
Bertl_oO
section 4
02:15
Bertl_oO
(but no template)
02:16
Bertl_oO
note that a CV (and in this case the proposal) is like a business card ... you basically get one chance to make a first impression there
02:17
Bertl_oO
so you want it to look nice, be well structured and layed out and of course, on the point
02:46
Bertl_oO
off to bed now ... have a good one everyone!
02:46
Bertl_oO
changed nick to: Bertl_zZ
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se6astian|away
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BAndiT1983|away
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se6astian
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parimal
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BAndiT1983
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13:07
Bertl_zZ
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13:07
Bertl
morning folks!
13:20
kingsocarso
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14:34
parimal
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14:38
parimal
Hello Bertl
14:39
parimal
I emailed you my github repo link for T872, would you please have a look and give some feedback when free? :)
14:42
Bertl
sure, but for C++ you want BAndiT1983 to check
14:42
parimal
Oh okay, I will forward him the link too
14:43
Bertl
personally I'd work on the code formatting as it has some problems
14:44
Bertl
like for example in the Debayer.cpp lines 99, 102, 106, etc
14:45
BAndiT1983|away
changed nick to: BAndiT1983
14:48
parimal
Hello BAndiT1983, I sent you an email with my repo link for T872, would you please have a look?
14:50
parimal
Bertl, yeah I will fix the formatting issues right away, anything else?
14:57
Bertl
nothing from my side but I only skimmed over it
14:58
BAndiT1983
hi parimal, i've seen the email, but will check the code later, first finding, please adjust classes according to OOP, e.g. you have everything public in some of them
14:59
parimal
Oh alright!
14:59
parimal
Will fix it
15:00
BAndiT1983
do you need more info on that? or do you know what i mean?
15:00
parimal
yes, in my BMP class file everything is public, or did you mean some other file?
15:01
parimal
I meant BMP header file *
15:02
BAndiT1983
maybe it was BMP class, haven't inspected closer yet, but it's violating the principles of OOP and can be dangerous in real applications
15:02
BAndiT1983
will give you more findings later, by mail
15:03
parimal
yes I should have known better, will work on it :)
15:03
parimal
and okay, thanks for your time
15:03
BAndiT1983
no problem, if oyu have questions, then don't hesitate to ask
15:03
BAndiT1983
*you
15:04
parimal
yes, for our project proposal, we also need to add a timeline. Any hints on how accurate that needs to be?
15:05
BAndiT1983
if possible on weekly base
15:05
BAndiT1983
as we have to grade after every month, so you should try to create a plan for each of 12 weeks or so
15:07
parimal
Oh alright, thanks, I am interested in T763, will study it more and get back to you
15:08
BAndiT1983
please read logs from last days, there were some infos for that task
15:08
parimal
oh okay sure I will have a look
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se6astian|away
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parimal
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BAndiT1983
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BAndiT1983|away
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BAndiT1983|away
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20:47
se6astian
off to bed now
20:47
se6astian
good night
20:47
se6astian
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20:48
Bertl
nn
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