#apertus IRC Channel Logs

also looking at axihp_writer.vhd is there any reason to not start write data transactions indepentent of the address transactions?

what do you mean by 'write interleaving'?

and then transfering the data for those burst's interleaved

(obviously for the write transactions you would have to set wid to the corresponding awid)

i guess it could improve a interconnect a bit

well looking at the line linked above, could active not be replaced by enabled?

when you want to reload the FPGA config, you need to make sure that there are no outstanding transactions

(except for a reboot)

for the interleaving part, the limiting factor is typically the bandwidth on the AXI master, so not sure what interleaved transactions would help

yeah thinking a bit more about it, it probably wouldn't do much

something I really missed back then :)

yeah the axi checker seems quite nice

the current in-flight transactions are counted in 'active'

i.e. addresses submitted for a data transaction

this allows to align address and data when shutting down the writers

it might not be the most elegant solution, but it certainly worked :)

after reload you already lost

well you could read the fifo level

SAXIHP{0-3}RCOUNT[7:0]

and also SAXIHP{0-3}WACOUNT[5:0]

hmm, might work

or somehow terminate the transactions (which I do not know if it is possible)

what are your plans on the AXI (writer/reader) side?

well if DATA is missing you could just issue some addresses, these could even point to somewhere non existant, because as far as i can tell it should still complete the transaction

anuejn and me have been thinking of rewriting the gateware in nmigen

ah, so that is preparations for a migen AXI gateway

or probably more a bridge

for things like configurations stuff a high level api would be quite nice where you just say these are configuration registers, map them to these addresses

well looking at SAXIHP{0-3}WCOUNT[7:0] would probably yield a interesting datapoint for benchmarking them

*backbone

yes, that is a good idea

oh yeah, had the same problem the other way around

using the ACP port completely starves the cpu

how are you setting the priority atm?

IIRC, the bus side is kind of ignored (not implemented) on the Zynq

but that's handwaving, I'd have to check the stuff we tried back then

that'd be really great! :)

hello Bertl :)

I have speed up my code some more i reached 257 mhz on maxv

real

I meant by real that I have run my code on "Quartus Prime Lite Edition " on maxv fpga

ah, so simulation (at best)

sorry for that :)

do you *

modelSim

yeah ok after placement and routing :)

is the code up-to-date and easy on the eyes?

nah, doesn't look like the github repo is up-to-date

iam pushing the code right now :)

I distributed the long input logic gates to be in a pipeline form as the max input to any logic gate is 2 inputs

and the worst paths are in those gates

is that the max words in one line ? or something else ?

but when i sample on both edges the speed drooped to half

GENERIC and the space :/

so if you manage to get to 150MHz, you are already processing 300MHz worth of data

so, what's wrong in line 38?

yes missing a space

actually there is the missing space :)

lines 100-105?

separators like ';' or ',' only get a space after them

oeprators get spaces around the operators

one acceptable exception to that is arithmetic stuff like SIZE-1

so what's wrong in lines 90-156?

yeah, that and something else, which is also a problem in lines 19-88 :)

indentation is missing there

the parts inside are, well, 'inside' so should have one level of indentation

but I'm not even considering those details at the moment

yep, and personally I'd put the generic in a single line

s/single/separate/

yep

but that's okay was just for your information

well, that's why I'm pointing out all the problems now and not after your submission :)

you're welcome!

missing a space

bingo :)

yes, try that as well as wrapping everything into a commandline build and test suite setup

a do file or a testbench

whatever works is fine

yeah those GUIs are killing me and Iam working with command lines

I have a doubt, In the task it is written that we can assume input clock of 100MHz but we have to receive data at both edges of 300 MHz clock.

that is a good observation, but the task also says that you can use 'magic stuff' the FPGA manufacturers provide (for free) like DDR or in this case PLL/MMCM

Actually I am trying to avoid any manufacturer's stuff.

so be it

not from our side, but IIRC, GSoC always hase some 'basic' templates

https://wiki.apertus.org/index.php/GSoC_Overview

(but no template)

so you want it to look nice, be well structured and layed out and of course, on the point

I emailed you my github repo link for T872, would you please have a look and give some feedback when free? :)

Oh okay, I will forward him the link too

like for example in the Debayer.cpp lines 99, 102, 106, etc

Hello BAndiT1983, I sent you an email with my repo link for T872, would you please have a look?

nothing from my side but I only skimmed over it

Oh alright!

do you need more info on that? or do you know what i mean?

I meant BMP header file *

will give you more findings later, by mail

and okay, thanks for your time

*you

if possible on weekly base

Oh alright, thanks, I am interested in T763, will study it more and get back to you

oh okay sure I will have a look

off to bed now