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#apertus IRC Channel Logs

2018/01/23

Timezone: UTC

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rton
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Bertl_oO
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se6astian|away
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07:07
se6astian
GSoC Org application deadline is today
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07:07
se6astian
we have successfully completed our application
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pusle
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seku_
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Guest98629
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fredy
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Bertl_zZ
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rton
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seku_
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seku_
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seku_
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BAndiT1983|away
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seku_
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seku_
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se6astian
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seku_
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manas
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13:56
manas
Hello
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13:56
manas
I saw the update on the FPGA challenge page
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13:57
manas
I made a VHDL code for PWM generator.
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13:57
manas
https://github.com/Manas173/PWM-generator-and-I2C_slave/blob/master/generator.vhd
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13:58
manas
It's taking in the duty cycle and producing a PWM...the output is in the STD_LOGIC form, I even provided two test benches.
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13:59
manas
Just a question: Do I need to generate the PWM output in STD_LOGIC_VECTOR or the code is fine?
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14:00
manas
I even did the I2C slave module...Can check in this link
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manas
https://github.com/Manas173/PWM-generator-and-I2C_slave/find/master?q=
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14:04
manas
If everythings okay then I go with connecting both modules
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manas
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rton
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18:58
Kjetil
interesting indentation
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comradekingu
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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seku
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BAndiT1983
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