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#apertus IRC Channel Logs

2016/11/22

Timezone: UTC


23:09
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23:22
Bertl
off to bed now ... have a good one everyone!
23:22
Bertl
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Bertl_zZ
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05:40
Bertl
morning folks!
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se6astian|away
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06:42
se6astian
good day
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se6astian|away
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philgrandeC
morning folks, morning bertl
08:51
philgrandeC
btw, i am fine. Thanks for asking (4 days ago;). Didnt check the irc anymore on that day
08:51
Bertl
good to know :)
08:51
philgrandeC
How's it going in vienna?
08:52
Bertl
no idea :)
08:52
philgrandeC
where u at?
08:52
Bertl
Laaben
08:52
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08:53
philgrandeC
had to search that first, to be honest
08:53
Bertl
kind of expected :)
08:55
philgrandeC
I just stumbled about t652 at phabricator
08:56
philgrandeC
do you still follow that approach?
08:56
Bertl
which one?
08:56
philgrandeC
the micro-sd raid
08:57
Bertl
we did a test plugin for up to three SD cards but we haven't had the time to write any software to test it yet
08:58
philgrandeC
can imagine. When i first saw the 4k burst on the first beta pictures, i thought about that kind of array, but never found the topic or point to ask you for
08:59
philgrandeC
what write speed do we/you have to aim at to make it reasonable?
08:59
mithro
Is anyone here going to 33C3?
09:00
Bertl
it has to be around 50Mbyte/s per card to make sense
09:00
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09:01
philgrandeC
And then we'll end up in an raid 0 around 120/130Mbyte/s? or could we even reach the 150? Depends on controller i gues
09:01
philgrandeC
*guess
09:01
philgrandeC
Hey mithro
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09:02
Bertl
yeah, well, in the test setup, the controller will be in the FPGA
09:02
philgrandeC
dunno jet, i'll hardly find the time
09:04
philgrandeC
the axiom project really reminds me hardly to the point when i quitted my informatics studies, dropped programming (vbasic,c++,some lil java,) just whe i got a clue what ruby might become..
09:06
philgrandeC
later on there might be a seperate controller-modul?
09:07
Bertl
yeah, if that works as expected, a smaller FPGA will be added as controller to a larger module (several cards)
09:07
philgrandeC
or is the fpga capable to handle the data controlling by the way
09:07
Bertl
there aren't enough IOs available for a large raid, so we need some gearwork
09:08
philgrandeC
guess so..
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philgrandeC_
With not enough IO's you mean physically on the fpga, not the data bandwith with processor-interface board v1?
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philgrandeC_
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mandresc
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09:25
[philgrandeC]
do you have a link to the fpga schematics? I am scrolling through lab and wiki, reading many interesting things, but iam afraid to loose myself between all those unseen topics
09:26
Bertl
what schematics do you refer to? the MicroZed?
09:26
BogdanXor
prob. http://zedboard.org/sites/default/files/documentations/MicroZed_RevB_Schematic_130617_0.pdf
09:27
Bertl
we use RevF, but otherwise, yes
09:27
BogdanXor
or maybe http://zedboard.org/sites/default/files/documentations/MicroZed_Rev_F_Schematic_141212.pdf
09:27
BogdanXor
yea
09:28
[philgrandeC]
thanks for the shortcut - now im stuck in http://zedboard.org/sites/default/files/documentations/MicroZed_HW_UG_v1_6.pdf
09:28
[philgrandeC]
;P
09:29
[philgrandeC]
should have read this in the last two years, instead of annoying for news ;)
09:32
[philgrandeC]
So, have a good day - seems like i'll have something to study. To get a glimpse what the core team is dealing with every day - Thanks for the link and answers
09:32
Bertl
you're welcome!
09:34
BogdanXor
MicroZed - with Zynq?! I wonder why I had the impression the hardware was based around a Kintex 7 FPGA
09:35
BogdanXor
like the most powerful one that the free Xilinx Vivado license could support
09:36
BogdanXor
ah, it was the preprocessing module of the Gamma that will be using that - https://wiki.apertus.org/index.php/AXIOM_Gamma
09:37
BogdanXor
will you guys develop a custom board for that, or would you use something pre-made?
09:39
BogdanXor
or maybe something like http://www2.hdl.co.jp/en/index.php?id=302 ?
09:41
Bertl
for the Gamma we developed a custom board
11:46
Bertl
off for now ... bbl
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Bertl
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Guest26960
bertl?
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