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#apertus IRC Channel Logs

2019/07/22

Timezone: UTC


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Bertl
morning folks!
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shebin_joseph
hello
07:28
Bertl
off to the hub now ... bbl
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Bertl
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shebin_joseph
i want to use systemd,Is arch linux distro good beginner ?I am totally new to linux
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SHEBIN_JOSEPH
HELLO
12:29
SHEBIN_JOSEPH
is it okay,if I install arch linux in a virual machine than my real pc
12:29
SHEBIN_JOSEPH
will systemd works fine in virual machine ?
12:30
SHEBIN_JOSEPH
which is the best virtual machine to install arch linux in windows 10 ?
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Bertl_oO
SHEBIN_JOSEPH: I have no clue whatsoever about windows 10 :)
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Dev_
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13:23
Dev_
Hello BAndiT1983, Are you available right now ?
13:25
Dev_
I wanted to ask where should the whole frameserver module to be placed,
13:26
Dev_
I was placing it in processingTest so that we can have access of all the info related to frames from processingPresenter
13:32
Dev_
Also , we need a class which can be used to interact with frameServer UI . Can we use the presenter class for this purpose or another class need to be build for this purpose.
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BAndiT1983
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16:17
Y_G
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16:21
BAndiT1983
hi Y_G, what's new?
16:23
Y_G
Hi BAndiT1983, Changing the packet structure rn for adding DaemonRequest.
16:24
BAndiT1983
any issues so far?
16:26
Y_G
None at the moment
16:30
se6astian
hi Y_G we have currently taken the remote beta out of the darkbox
16:30
se6astian
it will be reinstalled in 1-2h at the latest
16:30
BAndiT1983
are tests ongoing or some modifications?
16:31
se6astian
mechanical discussions
16:31
Y_G
Ok, se6astian
16:36
dev__
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16:37
dev__
Hello BAndiT1983 , are u available ? ,
16:38
BAndiT1983
hi dev__
16:38
dev__
I wanted to ask where should the whole frameserver module to be placed, I was placing it in processingTest so that we can have access of all the info related to frames from processingPresenter
16:39
BAndiT1983
why should it be placed? isn't this info coming from OCcore?
16:39
BAndiT1983
*placed there
16:40
dev__
Yes,
16:40
BAndiT1983
have you seen my trello comment and the text diagram?
16:40
dev__
So we will be making it as a separate module , just like processingTest, OCBackup ...
16:41
BAndiT1983
it was the plan from the beginning of the frame server project
16:41
BAndiT1983
what's the point of using processingtest to place frame server there?
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Dev
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16:46
dev__
understood,
16:47
BAndiT1983
which data would you use from precessingtest for frame server?
16:47
BAndiT1983
*processingtest
16:49
dev__
I was trying to make presenter(currently being used in processingTest) like structure for frameserver, So I was thinking that if it is possible to use the data which it (presenter) have , like name of loaded file, parameters of any frame
16:50
BAndiT1983
but all of this has to be handled by frame server and not mixed into another module
16:51
dev__
yes, Frameserver should be treated as separate module, it Will contain it own Presenter class which will be reposible for interacting with UI
16:51
dev__
it's
16:55
dev__
I wanted to ask about event bus, It will be used for registering callbacks and fire them, I wanted to ask how these events will be registered
16:56
BAndiT1983
example is in ProgressDialogPresenter, code is rather old, but should still be ok for general tests
16:56
dev__
like we have an event like Quality Parameter for Downscaler
16:57
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Bertl_oO
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17:00
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17:00
se6astian
meeting time
17:00
se6astian
welcome everyone
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17:02
supsraj
Hello :)
17:02
BAndiT1983
hi
17:04
se6astian
Nira please start your report
17:04
Nira
hi everyone
17:05
Nira
this week I have been learning about SPI, so how to use it on PIC16 and PIC32 for both to communicate, so for sending this way the "fake" pulses to check if the debouncing done until now works or not
17:05
Nira
I have written the SPI configuration on the PIC16 and have been checking how to do it on the PIC32, but I have many doubts, so maybe after the meeting Bertl can help me with this
17:06
Bertl
sure, any code to look at?
17:07
Nira
yes, I will send it after the meeting
17:07
Nira
I know that I should have asked for help before, sorry..
17:07
Nira
so that would be all
17:08
se6astian
many thanks for the report
17:08
se6astian
Fares: your turn!
17:08
Fares
Hi everyone
17:10
Fares
Early this week I fixed few bugs in Axihp_reader|writer and it is now working but still the last few bytes of data is corrupted, I still need to work in that, but for now the xilinx dma module working perfectly with it for testing purposes
17:10
Fares
Then I worked in the software side, I extended the challenge code to generate different lj92 files to be used for testing the core
17:11
Fares
And I also wrote a python code to test the core in zynq and drive the dma, but it was very slow so I moved it to c++ and it is completed but not yet tested
17:12
Bertl
okay, so what are the plans now?
17:13
Fares
So next week will be testing it and finish the documentation so anyone can reproduce the results and test the core, and also will work on extending the lj92 decoder which is used in MagicLantern projects including MLV APP
17:14
Bertl
sounds good!
17:14
Fares
That would be all from my side, thank you!
17:14
se6astian
many thanks
17:15
se6astian
anyone else here, Y_G, dev__, apurvanandan[m] ?
17:15
se6astian
aSobhy: ?
17:15
aSobhy
I'm here
17:16
apurvanandan[m]
Yes, I am here
17:16
se6astian
apurvanandan[m]: please go ahead
17:17
apurvanandan[m]
Hi everybody,
17:20
apurvanandan[m]
This week I overcame the problem I stuck at from quite some time. I am able to receive all the words correctly from the Virtex-5 fpga ( transmitter) and there are no errors in transitions of the words. So I am receiving both the words correctly. Now I am removing previous CDC gearing and attaching a FIFO that will remain in underrun.
17:20
supsraj
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17:21
apurvanandan[m]
The issue was I had switched on dynamic update of delay which wasn't required!
17:22
apurvanandan[m]
After changing the FIFO ( will be done in few hours) the whole gearwork will be ready but for one LVDS
17:23
apurvanandan[m]
After that I will move to using all LVDS channels and their channel bonding, I have plans ready for it.
17:23
Bertl
okay, keep in mind, the BER testings are mandatory
17:24
apurvanandan[m]
Tonight I will report the correct BER of this connection from hardware
17:24
Bertl
looking forward to it! :)
17:25
apurvanandan[m]
Thanks, for supportBertl . I have taken speed now :)
17:25
apurvanandan[m]
This is all from my side, thanks for the time
17:25
Bertl
perfect! thanks!
17:26
se6astian
great, thanks!
17:26
se6astian
dev_ your turn
17:26
dev__
Yes se6astian
17:26
dev__
hello Everyone
17:26
dev__
last week, I could able to make a fusehandler for frameserver, but haven't tested it yet and fixed tight coupling issue in allocators.
17:27
dev__
after that , I placed a tentative structure of frameserver in OC (wrongly placed in processingTest and pointed by mentors, I will Fix it).
17:27
dev__
Other time was spent for thinking how eventbus will be used, Frameserver presenter will be made etc.
17:27
dev__
This week , I will be working to make Frameserver presenter for interacting with UI.
17:28
dev__
That's it from my side
17:28
se6astian
thanks
17:29
se6astian
aSobhy: please go ahead
17:29
aSobhy
Hello everyone, the past week I was fixing a lot of synchronization errors and consumed a lot of time in understanding how "alignwd" in the CLKDIVC & IDDRx4B modules is working and failed. I checked my code with apurvanandan[m] the code and we almost using the same thing but it didn't work at my side.
17:29
aSobhy
all the rest modules works fine except that part. I hope I fix it ASAP.
17:29
Bertl
okay
17:30
Bertl
anyting else?
17:30
aSobhy
yeah I want your advice after the meeting
17:31
se6astian
many thanks!
17:31
se6astian
Y_G: your turn
17:31
Y_G
Hi all,
17:31
Y_G
This week I was mostly fixing some bugs regarding i2c `set` `get` from DaemonCLI. I have it fixed but then the code seemed too bulky as most set/get functions require atmost 2 parameters as of now and i2c set/get required 4 parameters.So decided to create a seperate packet for i2c requests. Working on that part now
17:32
Y_G
In the upcoming week I would work on testing things with dummy WebUI as packet structure has changed, and I have done no testing at all through Web UI.
17:32
Y_G
That would be it from my side
17:33
se6astian
thanks!
17:33
se6astian
anyone else have something to report?
17:35
se6astian
right then I will do a very brief update because we are in the middle of a big mechanical design and hardware design meeting at the axiom office right now
17:35
se6astian
we will shoot the next team talk on thursday
17:36
se6astian
we received some alumnium parts of the enclosure we had anodized separately
17:36
se6astian
we will also feature them in the team talk update video
17:37
se6astian
many thanks everyone
17:37
se6astian
remember second gsoc eval period is very soon
17:37
se6astian
starting today
17:37
se6astian
ending friday
17:37
se6astian
so see you next week for the irc meeting at the latest
17:38
se6astian
feel free to discuss detials with your mentor, etc. now
17:41
aSobhy
Bertl are you available now or after the meeting that se6astian mentioning ?
17:43
Bertl
I'll be on the road shortly (for about an hour) but we can chat till then and afterwards
17:44
aSobhy
Ok no problem
17:44
dev__
supragya_, and BAndiT1983 I will be making a frameserver presenter. It will contain methods like setting debayering algorithm, setting quality parameters , framespersec etc. It will take required info of frames by loading first frame etc. please guide me if i miss something or need to be taken care of
17:45
BAndiT1983
where will you place frameserver presenter?
17:45
dev__
in frameserver module.
17:46
BAndiT1983
what do you need to do to implement such a module?
17:47
dev__
The frameserver module ??
17:47
BAndiT1983
yes
17:48
dev__
It will interact with OCcore and take processed output to some media player using some virtual avi file
17:49
BAndiT1983
this doesn't answer my question, i know the theory all too well, as i was one of the people who have created the task
17:50
dev__
yes
17:51
dev__
Can u please tell me what is your thought ?
17:51
dev__
upon this
17:52
se6astian
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17:52
BAndiT1983
i wanted to know which steps you will take to implement the frame server module, there are some necessary steps to do to create a new module
17:57
dev__
okay, The module will contain AVIEncode(to make virtual avi file), FrameserverPresenter (to interact with OCcore and OCui). The Ui will reside in OCui. And this will work as an integrated sytem
17:58
BAndiT1983
this are not the steps i mean, but merely general descriptions of what it will contain
17:58
dev__
I have to take care of MVP model which u pointed out earilier during this
17:58
BAndiT1983
UI cannot reside in OCui, as it has to be placed in the module
17:59
dev__
okay.
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Fares
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18:02
dev__
I don't have much clear idea about step but here are some them which i can think of 1) I will make add Ui component using QT 2) After That I will go for making an presenter class for intraction 3) I will try to use inputs from Ui to create an AVI file 4 ) Setting up Fusehandler correctly and then try to frameserver the data
18:03
BAndiT1983
you are missing a couple of tests, which have to be taken care of for a new module, what i read here are just general descriptions and nothing specific to my question
18:03
BAndiT1983
*-tests +steps
18:05
dev__
U mean, unit testing. just like we have for debayering algos and downscaler etc , yes ?
18:06
BAndiT1983
no, i still mean steps, tests was a typo as i'm developing something else in parallel and strayed off in my thoughts
18:06
Bertl
off for now ... bbl
18:07
Bertl
changed nick to: Bertl_oO
18:08
dev__
it would be helpful if u please point out something
18:09
dev__
As I don't have in depth steps info yet
18:09
BAndiT1983
but it was your task to get familiar with OC, if i tell you all the steps, then i can sit down myself and develop this things
18:10
BAndiT1983
haven't you looked how OCLauncher was created or first commits of OCBackup?
18:10
dev__
I have to will see
18:12
dev__
Yes, I will think about it. i will provide u with a document which will contain all the steps and then it would be easy to point out missing things
18:12
dev__
till tomorrow
18:19
dev__
Thanks for your time, I will update u soon.
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dev__
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RexOrCine
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Fares
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19:06
BAndiT1983
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19:12
Bertl_oO
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19:12
Bertl
back now ...
19:13
Bertl
aSobhy: we can talk anytime
19:14
apurvanandan[m]
Hey Bertl, So we don't need full or almost full checks in direct connection?
19:15
Bertl
depends on your clock rates, but in the discussed case (generator at 60MHz, FTDI interface at 100MHz) there is no way for the FIFO to get full
19:15
apurvanandan[m]
direct connection of the ends of FIFO to gearing and FT601
19:16
Bertl
what gearing :)
19:16
apurvanandan[m]
Ok , so I will set some ideal almost empty point around 32 words out 512 depth and try to maintain that position
19:17
apurvanandan[m]
Simple 8 byte received + PRNG word + rest zeroes
19:17
apurvanandan[m]
At 60MHz
19:17
apurvanandan[m]
Sorry I mean 1 byte /8bits
19:17
Bertl
so combination not gearing
19:18
apurvanandan[m]
Yes
19:18
apurvanandan[m]
PRNG is clocked at rate of words received so they can be direct concatenated right?
19:19
Bertl
does the FIFO have delays on the empty output?
19:26
apurvanandan[m]
Upon reading the documentation, it can have delay of one clock cycles
19:26
apurvanandan[m]
Haven't read the memory guide completely.
19:32
BAndiT1983|away
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19:35
Bertl
well, time to read up on the FIFO then :)
19:40
aSobhy
here is what I'm getting alignwd changing the sample edge actually sample the word 1 cycle later
19:40
aSobhy
what happens is the first time i raise the alignwd signal and changes the sampling edge and the sclk lower cycle expands one cycle and thats true
19:40
aSobhy
whenever I raised the alignwd again it doesn't response to it
19:42
aSobhy
Is their another way to do word alignment?
19:43
Bertl
I'm not sure what you are talking about, care to give some context, preferably HDL code to look at?
19:48
aSobhy
here it is the link of the code
19:49
aSobhy
https://github.com/aabdosobhy/Bi-Direction-packet-protocol/blob/master/Training/RFW/train.vhd
19:51
aSobhy
I'm simulating the code right I'll take a screenshot of it now
19:51
aSobhy
right now**
19:51
Bertl
again, everything is all over the place, no proper indentation, etc
19:54
aSobhy
I removed the comments on hurry
19:56
se6astian|away
changed nick to: se6astian
20:02
aSobhy
now its formatted
20:05
Bertl
so, I see that your 'deserializer' blackbox connects to the alignwd of the clock divider
20:07
aSobhy
yes I raise the alignwd in the deserializer
20:07
Bertl
for how many clock cycles?
20:07
aSobhy
for one cycle of e_clk
20:08
Bertl
and did you check with the design guide if that is okay?
20:11
aSobhy
the only description I found is "Word alignment control signal, active high. (ALIGNWD can be asynchronous to the ECLK domain, but it must be at least two ECLK cycles wide.)
20:11
aSobhy
"
20:12
Bertl
so you made it one e_clk cycle, yes?
20:12
aSobhy
and when I try to raise it all the falling edge of the sclk ( = 2 e_clk )that It doesn't respond to it ever
20:12
aSobhy
>= *
20:14
Bertl
how did you verify that?
20:14
Y_G
left the channel
20:15
aSobhy
with my eye!
20:15
Bertl
so you have a fast eye, yes? :)
20:15
aSobhy
I traced it many times
20:15
aSobhy
no I'm simulating it cycle by cycle
20:15
Bertl
how?
20:16
aSobhy
on modelsim
20:16
Bertl
with the netlist from?
20:17
aSobhy
I generated the libraries of machxo2 to use them on modelsim
20:17
aSobhy
is that what you mean ?
20:17
Bertl
well, that's a step in the right direction
20:17
Bertl
what I actually expect is something like:
20:18
Bertl
"here is the minimal code I wrote to test and simulate the CLKDIVC hack I'm working on"
20:18
Bertl
"here are the steps to reproduce the issue"
20:19
Bertl
then I can take a look at it and probably figure out where the problem is
20:20
aSobhy
I'm didn't catch you !
20:21
aSobhy
their is a do file I wrote If you want to see it
20:22
Bertl
the problem you have is with the CLKDIVC, right?
20:22
aSobhy
yes
20:22
Bertl
so first step is to remove everything else from the equation
20:23
Bertl
write a short example which just uses the CLKDIVC with a little logic to trigger the problem
20:23
aSobhy
simulate the CLKDIVC alone ?
20:23
Bertl
this is what we call 'minimal code/example'
20:25
Bertl
if you ever want to report a bug or get some help from an FPGA vendor, you have to do that because nobody will spend time on picking apart your code to figure out where the problem is
20:25
aSobhy
I done it before simulated the file generated from lattice and see the results and it was hesitating.
20:26
Bertl
hesitating?
20:26
aSobhy
OK I'll do a minimal code for the CLKDIVC
20:27
aSobhy
one time it works and many times don't in the same simulation.
20:27
Bertl
got a VCD for that?
20:28
aSobhy
no
20:54
apurvanandan[m]
Should the data pause condition be prefered with fifo = empty or should be with fifo = almost_empty? I think almostempty will do bettter
20:54
apurvanandan[m]
Bertl: Ok I will read that pdf :)
21:14
Bertl
please explain why you think that 'almost empty' is better than 'empty' ...
21:16
apurvanandan[m]
Because it will maintained at ideal position fifo will never be completely empty or full
21:17
Bertl
how's that better?
21:17
Bertl
full is bad, that we can agree on, but empty?
21:18
apurvanandan[m]
Sorry, my bad
21:18
apurvanandan[m]
I got it
21:18
apurvanandan[m]
I was thinking in typical way
21:18
Bertl
there is one reason which might make almost_empty pfereable to empty
21:19
Bertl
that is if the empty signal comes delayed
21:19
Bertl
because then you have to delay your FTDI transmission for as long as you can be sure that the empty is valid
21:20
Bertl
OTOH, with the almost empty signal, you get an additional delay for the data and once your generator stops, data will get stuck in the FIFO
21:21
BAndiT1983
changed nick to: BAndiT1983|away
21:22
apurvanandan[m]
Yes, it is preferable in that way, i got it
21:58
se6astian
off to bed
21:58
se6astian
good night
21:58
se6astian
changed nick to: se6astian|away
21:58
Bertl
nn
23:20
apurvanandan[m]
Bertl, everything is setup and it is receiving very smooth when I transmit two words alternatingly (ABABAB...) words but when I switch to counter I get lot of error like before.
23:20
apurvanandan[m]
Here is raw data in both cases : https://pastebin.com/U6JCFvfy
23:21
apurvanandan[m]
https://pastebin.com/Nbt4QaFN
23:21
apurvanandan[m]
Please see if you are free
23:21
Bertl
what are the columns this time?
23:22
apurvanandan[m]
Last two colums are useful: Last column is counter on machXO2 and second last column is word received from Virtex 5
23:23
Bertl
again 8 bit only, yes?
23:23
apurvanandan[m]
Counter data has counter on both fpgas while alternating has counter on machXO2 and alternating ABABABAB... on Virtex 5
23:24
apurvanandan[m]
Yes
23:24
Bertl
so we still do not know the encoded values
23:25
apurvanandan[m]
I can attach encoded values too if you want but encoded values will be tough to read in counter?
23:25
apurvanandan[m]
Alternating data is perfect if you see
23:27
Bertl
well, it is okay for this specific case, that is all you can conclude
23:27
Bertl
and actually not even that, all you can tell is that the decoded value is correct
23:27
apurvanandan[m]
hmm, I see
23:28
apurvanandan[m]
I am attaching it in just two minutes
23:28
Bertl
for example, try with two alternating values from the counter
23:29
apurvanandan[m]
Alternating value from counter, what does that mean?
23:30
Bertl
your counter example shows C0, C1 for example going wrong
23:30
Bertl
so try C0, C1 alternating
23:31
apurvanandan[m]
Ok got it
00:06
aSobhy
Bertl I have generated the vcd file from modelsim
00:06
aSobhy
how to run it again in modelsim
00:06
Bertl
no idea, I don't use modelsim
00:06
aSobhy
I found "gtkwave" but didn't work
00:06
Bertl
that's what I normally use
00:07
Bertl
let's see the VCD file
00:07
aSobhy
ok I'll push it now
00:12
aSobhy
here it is:
00:12
aSobhy
https://github.com/aabdosobhy/Bi-Direction-packet-protocol/blob/test_CLKDIVC/Training/RFW/test_CLKDIVC.vcd
00:16
Bertl
looks fine in GTKWave
00:16
Bertl
but shows hat the word_align changes quite irregularily
00:17
Bertl
i.e. sometimes it is one clock cycle, at other times it is two cycles
00:18
aSobhy
yeah I meant that
00:19
Bertl
so your logic operating on word_align seems to be wrong then, no?
00:20
aSobhy
no the word alignment I used is like the first one I raised
00:20
Bertl
where is the code for this test?
00:20
Bertl
i.e. the HDL which generated this VCD
00:21
aSobhy
https://github.com/aabdosobhy/Bi-Direction-packet-protocol/blob/test_CLKDIVC/Training/RFW/test_CLKDIVC.vhd
00:22
aSobhy
it has only the CLKDIVC component that I'm using
00:22
Bertl
this doesn't show where the word_align is generated
00:22
Nira
changed nick to: Nira|away
00:23
aSobhy
I removed every thing and testing the CLKDIVC and simulating the alignwd at different positions
00:23
Bertl
so you intentionally simulated a 1clock cycle word_align?
00:23
aSobhy
let me show you what I meant by that simulation
00:24
aSobhy
the same position i raised the alignwd at 1000ps and 1500 ps
00:25
aSobhy
the first one increased the sclk by one cycle and the other don't
00:26
Bertl
both word_align pulses are only one cycle long
00:27
Bertl
(as can be seen on the VCD)
00:27
Bertl
they are also not at 1000ps and 1500ps but 1050ps and 1550ps FWIW
00:30
Bertl
you also set the DIV generic to 4.0 and messing with the word align in a way which goes against the documentation
00:31
aSobhy
ah sorry the time shifted at me
00:31
Bertl
so the simulation results might be accurate or they might be just wrong
00:31
aSobhy
when i try to raise it 2 cycles like at
00:31
Bertl
in any case, it is unlikely to give you the desired results
00:32
aSobhy
2600 & 3500
00:32
aSobhy
the first one works and the other didn't
00:33
aSobhy
ok I'll remove that part
00:34
aSobhy
what to use instead ?
00:35
Bertl
what do the examples in TN1203 use?
00:38
aSobhy
I'm downloading it now
00:39
aSobhy
ah yeah its the same file
00:40
aSobhy
Used CLKDIVC
00:40
Bertl
with some weird logic on word align?
00:42
aSobhy
mmmmm no !!
00:42
aSobhy
Its only input at the IDDR
00:43
Bertl
so why isn't that working for your purpose?
00:45
aSobhy
I thought it should be input for poth
00:45
aSobhy
both*
00:45
aSobhy
(CLKDIVC & IDDR)
00:47
Bertl
well, that is a good assumption, but you are also expecting a specific behaviour
00:49
aSobhy
as their will be two bits lost and two new bits so if I increased the sclk one eclk cycle the new 2 bits will be shifted
00:49
Bertl
the documentation says, among other things:
00:50
aSobhy
that's the behavior I believe
00:50
Bertl
for the x2/x4 gearings, ALIGNWD must be pulsed eight times to step through eight possible word orders
00:52
Bertl
doesn't say much about the CLKDIVC behaviour itself
00:53
aSobhy
didn't see that one
00:54
Bertl
so, probably a good way to test this setup and how alignwd works is to simulate the deserializer with a legal SCLK ratio
00:54
Bertl
and a well defined serial bitstream
00:55
aSobhy
OK
00:55
Bertl
then assert the alignwd for two clock cycles and see what happens on the parallel side
00:56
Bertl
note that the best approach is to have a period length which is a multiple of your gearing ratio/output
00:57
aSobhy
ok i'll do that now
00:58
aSobhy
thanks Bertl for your time :)
00:58
Bertl
no problem