#apertus IRC Channel Logs

morning folks!

hello

HELLO

will systemd works fine in virual machine ?

Hello BAndiT1983, Are you available right now ?

I was placing it in processingTest so that we can have access of all the info related to frames from processingPresenter

Hi BAndiT1983, Changing the packet structure rn for adding DaemonRequest.

None at the moment

it will be reinstalled in 1-2h at the latest

mechanical discussions

hi dev__

why should it be placed? isn't this info coming from OCcore?

Yes,

So we will be making it as a separate module , just like processingTest, OCBackup ...

what's the point of using processingtest to place frame server there?

understood,

*processingtest

but all of this has to be handled by frame server and not mixed into another module

it's

example is in ProgressDialogPresenter, code is rather old, but should still be ok for general tests

welcome everyone

hi

hi everyone

I have written the SPI configuration on the PIC16 and have been checking how to do it on the PIC32, but I have many doubts, so maybe after the meeting Bertl can help me with this

yes, I will send it after the meeting

so that would be all

Fares: your turn!

Early this week I fixed few bugs in Axihp_reader|writer and it is now working but still the last few bytes of data is corrupted, I still need to work in that, but for now the xilinx dma module working perfectly with it for testing purposes

And I also wrote a python code to test the core in zynq and drive the dma, but it was very slow so I moved it to c++ and it is completed but not yet tested

So next week will be testing it and finish the documentation so anyone can reproduce the results and test the core, and also will work on extending the lj92 decoder which is used in MagicLantern projects including MLV APP

That would be all from my side, thank you!

anyone else here, Y_G, dev__, apurvanandan[m] ?

I'm here

apurvanandan[m]: please go ahead

This week I overcame the problem I stuck at from quite some time. I am able to receive all the words correctly from the Virtex-5 fpga ( transmitter) and there are no errors in transitions of the words. So I am receiving both the words correctly. Now I am removing previous CDC gearing and attaching a FIFO that will remain in underrun.

The issue was I had switched on dynamic update of delay which wasn't required!

After that I will move to using all LVDS channels and their channel bonding, I have plans ready for it.

Tonight I will report the correct BER of this connection from hardware

Thanks, for supportBertl . I have taken speed now :)

perfect! thanks!

dev_ your turn

hello Everyone

after that , I placed a tentative structure of frameserver in OC (wrongly placed in processingTest and pointed by mentors, I will Fix it).

This week , I will be working to make Frameserver presenter for interacting with UI.

thanks

Hello everyone, the past week I was fixing a lot of synchronization errors and consumed a lot of time in understanding how "alignwd" in the CLKDIVC & IDDRx4B modules is working and failed. I checked my code with apurvanandan[m] the code and we almost using the same thing but it didn't work at my side.

okay

yeah I want your advice after the meeting

Y_G: your turn

This week I was mostly fixing some bugs regarding i2c `set` `get` from DaemonCLI. I have it fixed but then the code seemed too bulky as most set/get functions require atmost 2 parameters as of now and i2c set/get required 4 parameters.So decided to create a seperate packet for i2c requests. Working on that part now

That would be it from my side

anyone else have something to report?

we will shoot the next team talk on thursday

we will also feature them in the team talk update video

remember second gsoc eval period is very soon

ending friday

feel free to discuss detials with your mentor, etc. now

I'll be on the road shortly (for about an hour) but we can chat till then and afterwards

supragya_, and BAndiT1983 I will be making a frameserver presenter. It will contain methods like setting debayering algorithm, setting quality parameters , framespersec etc. It will take required info of frames by loading first frame etc. please guide me if i miss something or need to be taken care of

in frameserver module.

The frameserver module ??

It will interact with OCcore and take processed output to some media player using some virtual avi file

yes

upon this

i wanted to know which steps you will take to implement the frame server module, there are some necessary steps to do to create a new module

this are not the steps i mean, but merely general descriptions of what it will contain

UI cannot reside in OCui, as it has to be placed in the module

I don't have much clear idea about step but here are some them which i can think of 1) I will make add Ui component using QT 2) After That I will go for making an presenter class for intraction 3) I will try to use inputs from Ui to create an AVI file 4 ) Setting up Fusehandler correctly and then try to frameserver the data

*-tests +steps

no, i still mean steps, tests was a typo as i'm developing something else in parallel and strayed off in my thoughts

As I don't have in depth steps info yet

haven't you looked how OCLauncher was created or first commits of OCBackup?

Yes, I will think about it. i will provide u with a document which will contain all the steps and then it would be easy to point out missing things

Thanks for your time, I will update u soon.

aSobhy: we can talk anytime

depends on your clock rates, but in the discussed case (generator at 60MHz, FTDI interface at 100MHz) there is no way for the FIFO to get full

what gearing :)

Simple 8 byte received + PRNG word + rest zeroes

Sorry I mean 1 byte /8bits

Yes

does the FIFO have delays on the empty output?

Haven't read the memory guide completely.

well, time to read up on the FIFO then :)

what happens is the first time i raise the alignwd signal and changes the sampling edge and the sclk lower cycle expands one cycle and thats true

Is their another way to do word alignment?

here it is the link of the code

I'm simulating the code right I'll take a screenshot of it now

again, everything is all over the place, no proper indentation, etc

so, I see that your 'deserializer' blackbox connects to the alignwd of the clock divider

for how many clock cycles?

and did you check with the design guide if that is okay?

"

and when I try to raise it all the falling edge of the sclk ( = 2 e_clk )that It doesn't respond to it ever

how did you verify that?

with my eye!

I traced it many times

how?

with the netlist from?

is that what you mean ?

what I actually expect is something like:

"here are the steps to reproduce the issue"

I'm didn't catch you !

the problem you have is with the CLKDIVC, right?

so first step is to remove everything else from the equation

simulate the CLKDIVC alone ?

if you ever want to report a bug or get some help from an FPGA vendor, you have to do that because nobody will spend time on picking apart your code to figure out where the problem is

hesitating?

one time it works and many times don't in the same simulation.

no

Bertl: Ok I will read that pdf :)

Because it will maintained at ideal position fifo will never be completely empty or full

full is bad, that we can agree on, but empty?

I got it

there is one reason which might make almost_empty pfereable to empty

because then you have to delay your FTDI transmission for as long as you can be sure that the empty is valid

off to bed

Bertl, everything is setup and it is receiving very smooth when I transmit two words alternatingly (ABABAB...) words but when I switch to counter I get lot of error like before.

https://pastebin.com/Nbt4QaFN

what are the columns this time?

again 8 bit only, yes?

Yes

I can attach encoded values too if you want but encoded values will be tough to read in counter?

well, it is okay for this specific case, that is all you can conclude

hmm, I see

for example, try with two alternating values from the counter

your counter example shows C0, C1 for example going wrong

Ok got it

how to run it again in modelsim

I found "gtkwave" but didn't work

let's see the VCD file

here it is:

looks fine in GTKWave

i.e. sometimes it is one clock cycle, at other times it is two cycles

so your logic operating on word_align seems to be wrong then, no?

where is the code for this test?

https://github.com/aabdosobhy/Bi-Direction-packet-protocol/blob/test_CLKDIVC/Training/RFW/test_CLKDIVC.vhd

this doesn't show where the word_align is generated

I removed every thing and testing the CLKDIVC and simulating the alignwd at different positions

let me show you what I meant by that simulation

the first one increased the sclk by one cycle and the other don't

(as can be seen on the VCD)

you also set the DIV generic to 4.0 and messing with the word align in a way which goes against the documentation

so the simulation results might be accurate or they might be just wrong

in any case, it is unlikely to give you the desired results

the first one works and the other didn't

what to use instead ?

I'm downloading it now

Used CLKDIVC

mmmmm no !!

so why isn't that working for your purpose?

both*

well, that is a good assumption, but you are also expecting a specific behaviour

the documentation says, among other things:

for the x2/x4 gearings, ALIGNWD must be pulsed eight times to step through eight possible word orders

didn't see that one

and a well defined serial bitstream

then assert the alignwd for two clock cycles and see what happens on the parallel side

ok i'll do that now

no problem