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| 10:43 | Bertl | morning folks!
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| 13:53 | se6astian | and the apocs
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| 13:53 | se6astian | sorry, wrong window :)
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| 15:14 | felix_ | on https://wiki.apertus.org/index.php/4K_HDMI_Plugin_Module : i wonder if there are hdmi->dp converters for a hdmi input; adding an input to that board doesn't add much cost to the BOM
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| 15:16 | felix_ | for the output side i also wonder if the dp->hdmi converters work with long hdmi cables; the hdmi2usb project had some issues with long hdmi cables that could only be avoided without changing the hardware with using active hdmi cables
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| 15:27 | felix_ | after the sdi connectivity board being ready, making the 4k hdmi/dp connectivity board isn't that much work, since it is basicaly removing stuff from the sdi board design and adding a connector and possibly a level converter/line driver
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| 15:28 | felix_ | if someone does the research if a level converter/line driver is needed and which one would work, i'd do the design; i'd really wait until the sdi board is ready and fully tested though
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| 15:33 | felix_ | oh and if there's someone with some spare time (and possibly a bit of frustration tolerance), i'd like to have some kicad stuff upstreamed; mainly the patched qfn footprint generator that needed some patching to be useful
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| 15:34 | BogdanXOR | what is the status on the SDI module?
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| 15:36 | felix_ | i still need to create a proper axiom connector footprint and still have to do about 50% of the placing of components and about 80% of the routing. but the difficult parts should be done by now
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| 15:38 | felix_ | i basically have done about 70% of the local placing and 35% of the global placing; so i need to push around some function units on the pcb
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| 15:38 | felix_ | for the routing i have to swap some connections on the fpga and figure out how to route the clock to the gigabit transceiver
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| 15:39 | felix_ | the latter is probably the most tricky thing that still remains
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| 15:40 | felix_ | problem there is that layer 3 of the pcb is rather fragmented in that area and basically mgtavcc under the clock pins, but the 1.8v rail under the clock chip and routing fast signals over a dicontinuity on the plane below is a really bad idea
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| 15:41 | felix_ | have to do at least part of the routing of the clock on the bottom layer; the sdi signals on the top layer are much easier in that regard, since layer 2 is a non-segmented ground plane
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| 15:44 | felix_ | i probably didn't write that in this channel, but the placement of the decoupling capacitors beneath the fpga was surprisingly doable and the segmented power planes is only an issue for the gtp clock and not for the rest
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| 15:45 | felix_ | http://i.imgur.com/2IS2RTu.png not the current state, but not that different to the current state
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| 15:57 | BogdanXOR | when you mean placing of components and routing you mean on the fpga, right?
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| 15:57 | BogdanXOR | and what do you mean by local/global placing?
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| 15:58 | BogdanXOR | (I come from the world of Xilinx ISE/Vivado - and for what I usually did it was sufficient to use the built-in placer/router with its various strategies)
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| 16:00 | BogdanXOR | ah, judging from the picture you are referring to placing & routing on the PCB
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| 16:01 | felix_ | no, on the pcb
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| 16:01 | BogdanXOR | (got confused because I was under the impression that the module's hardware (PCB, etc) was done and that only the design/architecture on the FPGA was left)
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| 16:02 | felix_ | with local placement i mean putting the capacitors/resistors at the right place near the chips and with global placing i meant putting the chips with their passives in a good place on the pcb and also reducing the pcb size
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| 16:02 | felix_ | won't place the stuff in the fpga manually ;)
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| 16:04 | se6astian | BogdanXOR: we finished a prototype hardware for fpga development of the SDI plugin module around christmas, this is now the next stage of production (non-prototype) hardware
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| 16:04 | BogdanXOR | I see
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| 16:07 | BogdanXOR | yeah, I would have been surprised if there was an attempt to place the stuff on the fpga manually (I was more thinking about some subset of the components of the fpga anyways - which is something that happens sometimes, albeit very seldom)
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| 22:12 | se6astian | good night
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| 23:10 | Bertl_oO | off to bed now .. have a good one everyone!
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