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| 16:00 | Bertl | MEETING TIME!
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| 16:00 | Bertl | who is here and wants to report something?
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| 16:00 | Bertl | se6astian is still on the road and might join later.
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| 16:03 | Bertl | not much to report from my side this week, mostly planning and testing for the upcoming designs.
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| 16:06 | Bertl | okay then ...
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| 16:06 | Bertl | MEETING CONCLUDED!
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| 16:07 | Bertl | feel free to add your reports later ...
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| 21:24 | anuejn | I do not have a lot to report
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| 21:24 | anuejn | just one random experiment:
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| 21:25 | anuejn | I tried to implement wavelet transform for compression using pytorch
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| 21:25 | anuejn | to accelerate it using hardware accellerators for convolutional neuronal networks
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| 21:25 | anuejn | as wavelet transform is basically a convolution
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| 21:26 | anuejn | and the rockchip has dedicated hardware for that
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| 21:27 | anuejn | on my M1 npu I got over 400fps
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| 21:27 | anuejn | for a 3 level haar cineform wavelet
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| 21:27 | anuejn | (just the transform, no quantization or bit packing)
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| 21:28 | anuejn | but I still found it quite interesting that it is indeed possible to use that kind of hardware for that without much hassle
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| 21:28 | anuejn | additionally vup convinced me, that a mipi plugin module with the lp lines equal for all lanes would probably work with some limitations
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| 21:29 | anuejn | that means that we could collaborate to build such a plugin, Bertl
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| 21:31 | anuejn | based on either the xilinx or the lattice appnote for a resistor phy and some (possibly 74xx ic) for buffering the lp signals
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| 21:33 | anuejn | (the main limitation is that we cannot send arbitrary width frames)
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| 21:33 | anuejn | vup calculated, that e.g. 4096 is impossible but 4100 would work
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| 21:34 | anuejn | and we could easily use the extra width to transport metadata
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| 21:34 | anuejn | which would be nice in any case
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