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#apertus IRC Channel Logs

2020/02/22

Timezone: UTC


01:23
illwieckz
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01:25
rajdeep
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01:46
rajdeep
while building axiom remote visualizer, I'm getting this error
01:47
rajdeep
fatal error: 3rdParty/imgui/imgui.h: No such file or directory
01:47
rajdeep
#include "3rdParty/imgui/imgui.h"
01:52
Bertl_oO
rajdeep: please check with BAndiT1983|away when he's around again
01:55
rajdeep
Okay
02:08
rajdeep
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04:12
Bertl_oO
off to bed now ... have a good one everyone!
04:12
Bertl_oO
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beingalacrit
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09:17
BAndiT1983|away
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09:18
BAndiT1983
rajdeep: hi, you also need to initialize git sub-modules in the repo
09:20
BAndiT1983
updated task description with this step
10:22
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intracube
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12:41
Bertl_zZ
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12:41
Bertl
morning folks!
12:49
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12:56
codetronaut
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13:02
kunalghosh[m]
Hello everyone! I'm Kunal Ghosh, a Physics major in freshman year. I'm a hobbyist developer having experience with Linux Kernel and KVM. Looking forward to get selected as a GSoC student this year! ð
13:02
Bertl
hello kunalghosh[m]!
13:03
Bertl
any specific tasks which sparked your interest so far?
13:07
kunalghosh[m]
Hi Bertl , implementing JTAG/SPI for MatchXO2 board feels like something I'd want to do!
13:08
abist
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13:10
Bertl
so T729 then ... got a rough idea how the parts (kernel, MachXO2, etc) are connected?
13:14
kunalghosh[m]
I've cloned the source and looking at it now...
13:15
Bertl
more talking about the 'physical' connections than the software side here ... do you know how to read schematics?
13:17
kunalghosh[m]
Yes I've got the datasheet as well, will go though it..
13:18
Bertl
https://wiki.apertus.org/index.php/AXIOM_Beta/Camera_Structure
13:18
Bertl
the MachXO2 in question are located on the Main Board, and they are connected to a PIC microcontroller each
13:19
Bertl
the PIC itself connects to the main FPGA (Zynq 7020) on the MicroZed via I2C
13:20
Bertl
the Zynq is a 7 Series SoC which contains (besides the FPGA fabric) two hardened ARM cores running Linux
13:26
preeti
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13:31
illwieckz
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13:32
kunalghosh[m]
Thank you, I will look into everything to get a better idea, is that ok?
13:34
Bertl
sure, let us know if something is unclear or if you have any questions related to GSoC 2020
13:35
Bertl
also check the lab for updates and/or clarifications to the tasks on a regular basis
13:37
BAndiT1983
subscribing to it will send updates automatically
13:39
kunalghosh[m]
sure, thanks again.
13:39
Bertl
have fun!
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codetronaut
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abist
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codetronaut
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BAndiT1983
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14:32
MHosni
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abist
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15:50
MHosny
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15:50
MHosny
Hello!
15:51
MHosny
From your email I got the idea that the project timeline maybe as follows
15:52
MHosny
1- editing the settings modules to have a generic top module for the changing settings (may take time)
15:53
MHosny
nvm this :'D
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codetronaut
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BAndiT1983|away
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19:43
MHosny
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illwieckz
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illwieckz
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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