Current Server Time: 07:29 (Central Europe)

#apertus IRC Channel Logs

2019/08/21

Timezone: UTC


00:40
RexOrMatrix[m]
<se6ast1an "https://www.imdb.com/title/tt605"> Yeah I read about that. Think it's something to do with the Idyllwild Egg case. An egg shaped object from outer space landed in some woods and passing hill-walkers and camping types got probed.
00:47
RexOrMatrix[m]
BAndiT1983: Come to the Telegram group.
00:56
Nira
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01:06
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BAndiT1983|away
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BAndiT1983
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08:41
BAndiT1983|away
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09:00
Bertl_zZ
changed nick to: Bertl
09:00
Bertl
morning folks!
09:04
comradekingu
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10:23
BAndiT1983
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11:07
Nira|away
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11:40
BAndiT1983|away
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11:42
RexOrCine
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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14:16
aleb
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14:26
apurvanandan[m]
Hello Bertl, My BER Testing code is now working perfectly on remote beta at DDR x4 300 MHz with BER lower than 10^-12 :)
14:27
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14:28
Bertl
apurvanandan[m]: great! what was the problem?
14:28
apurvanandan[m]
The problem was: though MachXO2 all LVDS_P were connected to _N pins of MachXO2, On Zynq also the LVDS_2 and LVDS_3 were labelled opposite ie _P on _N and vice versa. So that made them correctly connected, hence I removed the not of signal on Lanes 2 and Lane 3 and it got working
14:29
apurvanandan[m]
TL;DR Not only machXO2 had opposite labelled pins but the Zynq also had this on LVDS2 and LVDS3 lanes
14:29
Bertl
you reported problems with LVDS_0 yesterday though?
14:30
apurvanandan[m]
I missunderstood the right one as wrong because two lanes next to it were wrong
14:30
Bertl
okay, what is the total datarate with the current setup?
14:30
apurvanandan[m]
The FT601 issue isn't resolved till yet, it needs further research
14:31
apurvanandan[m]
But the LVDS are giving 2.4Gbps bandwidth
14:31
Bertl
well, that needs some improvements as well then :)
14:31
apurvanandan[m]
And the DDR x4 still doesn't work at 375 MHz
14:32
apurvanandan[m]
Yes, I am here after GSoC. I will definitely make everything perfect
14:32
Nira
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14:33
Bertl
does the dynamic delay work as expected now?
14:33
aleb
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14:34
apurvanandan[m]
Delays are working as expected, The issue was that delay mode was set to ECLK_ALIGNED, I set that to USER_DEFINED. Now they obey the value set by me
14:34
apurvanandan[m]
0.01% BER at DELAY0 , and 10^-12 BER at DELAY8
14:34
apurvanandan[m]
Where each delay tap = 105 ps
14:34
Bertl
nice
14:35
Bertl
and did you try different delays at 350/375MHz yet?
14:35
apurvanandan[m]
Implying 8 delay taps = 840 ps = 1/4 * 3.333 ns
14:35
apurvanandan[m]
I tried delay settings at 375 MHz , but they didn't work
14:36
Bertl
means you always got bad BER or did it show some effect?
14:37
aleb
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14:37
apurvanandan[m]
Yes I didn't try all 32 values, let me do that please
15:37
apurvanandan[m]
Bertl, It is working, I forgot to change the timing contraints earlier, now the throughput is 2.94 Gbps as reported by FTDI chip
15:37
apurvanandan[m]
10^-12 BER at 375 MHz
15:37
Bertl
nice
15:38
apurvanandan[m]
Thanks
15:38
Bertl
that's over 5 LVDS channels plus one clock
15:38
apurvanandan[m]
Yupp
15:39
Bertl
and you are testing/using 8b10b at the moment, correct?
15:39
apurvanandan[m]
Yes, I am
15:39
Bertl
so the raw bandwidth is about 3.7Gbit
15:40
Bertl
you are also using the 8b10b control symbols I presume?
15:41
apurvanandan[m]
Yes I am using K28.5, but will add more funtionality
15:41
Bertl
what is K28.5 used for at the moment?
15:41
apurvanandan[m]
Just for word alignment, could have used 0000011111
15:42
Bertl
and is the BER on the 10bit or 8bit side of the encoder?
15:42
apurvanandan[m]
8 bit side
15:42
Bertl
okay, can you do 10bit BER checks as well?
15:43
apurvanandan[m]
Please allow me to do it after making documentation
15:43
apurvanandan[m]
I am short on time for it
15:43
Bertl
fair enough, focus on the documentation
15:45
sebix
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16:23
Bertl
off for now ... bbl
16:24
Bertl
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BAndiT1983|away
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BAndiT1983
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Nira|away
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20:23
se6ast1an
off to bed, good night
20:58
BAndiT1983|away
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23:56
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