| 00:40 | RexOrMatrix[m] | <se6ast1an "https://www.imdb.com/title/tt605"> Yeah I read about that. Think it's something to do with the Idyllwild Egg case. An egg shaped object from outer space landed in some woods and passing hill-walkers and camping types got probed.
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| 00:47 | RexOrMatrix[m] | BAndiT1983: Come to the Telegram group.
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| 09:00 | Bertl | morning folks!
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| 14:26 | apurvanandan[m] | Hello Bertl, My BER Testing code is now working perfectly on remote beta at DDR x4 300 MHz with BER lower than 10^-12 :)
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| 14:28 | Bertl | apurvanandan[m]: great! what was the problem?
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| 14:28 | apurvanandan[m] | The problem was: though MachXO2 all LVDS_P were connected to _N pins of MachXO2, On Zynq also the LVDS_2 and LVDS_3 were labelled opposite ie _P on _N and vice versa. So that made them correctly connected, hence I removed the not of signal on Lanes 2 and Lane 3 and it got working
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| 14:29 | apurvanandan[m] | TL;DR Not only machXO2 had opposite labelled pins but the Zynq also had this on LVDS2 and LVDS3 lanes
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| 14:29 | Bertl | you reported problems with LVDS_0 yesterday though?
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| 14:30 | apurvanandan[m] | I missunderstood the right one as wrong because two lanes next to it were wrong
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| 14:30 | Bertl | okay, what is the total datarate with the current setup?
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| 14:30 | apurvanandan[m] | The FT601 issue isn't resolved till yet, it needs further research
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| 14:31 | apurvanandan[m] | But the LVDS are giving 2.4Gbps bandwidth
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| 14:31 | Bertl | well, that needs some improvements as well then :)
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| 14:31 | apurvanandan[m] | And the DDR x4 still doesn't work at 375 MHz
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| 14:32 | apurvanandan[m] | Yes, I am here after GSoC. I will definitely make everything perfect
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| 14:33 | Bertl | does the dynamic delay work as expected now?
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| 14:34 | apurvanandan[m] | Delays are working as expected, The issue was that delay mode was set to ECLK_ALIGNED, I set that to USER_DEFINED. Now they obey the value set by me
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| 14:34 | apurvanandan[m] | 0.01% BER at DELAY0 , and 10^-12 BER at DELAY8
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| 14:34 | apurvanandan[m] | Where each delay tap = 105 ps
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| 14:34 | Bertl | nice
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| 14:35 | Bertl | and did you try different delays at 350/375MHz yet?
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| 14:35 | apurvanandan[m] | Implying 8 delay taps = 840 ps = 1/4 * 3.333 ns
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| 14:35 | apurvanandan[m] | I tried delay settings at 375 MHz , but they didn't work
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| 14:36 | Bertl | means you always got bad BER or did it show some effect?
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| 14:37 | apurvanandan[m] | Yes I didn't try all 32 values, let me do that please
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| 15:37 | apurvanandan[m] | Bertl, It is working, I forgot to change the timing contraints earlier, now the throughput is 2.94 Gbps as reported by FTDI chip
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| 15:37 | apurvanandan[m] | 10^-12 BER at 375 MHz
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| 15:37 | Bertl | nice
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| 15:38 | apurvanandan[m] | Thanks
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| 15:38 | Bertl | that's over 5 LVDS channels plus one clock
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| 15:38 | apurvanandan[m] | Yupp
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| 15:39 | Bertl | and you are testing/using 8b10b at the moment, correct?
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| 15:39 | apurvanandan[m] | Yes, I am
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| 15:39 | Bertl | so the raw bandwidth is about 3.7Gbit
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| 15:40 | Bertl | you are also using the 8b10b control symbols I presume?
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| 15:41 | apurvanandan[m] | Yes I am using K28.5, but will add more funtionality
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| 15:41 | Bertl | what is K28.5 used for at the moment?
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| 15:41 | apurvanandan[m] | Just for word alignment, could have used 0000011111
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| 15:42 | Bertl | and is the BER on the 10bit or 8bit side of the encoder?
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| 15:42 | apurvanandan[m] | 8 bit side
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| 15:42 | Bertl | okay, can you do 10bit BER checks as well?
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| 15:43 | apurvanandan[m] | Please allow me to do it after making documentation
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| 15:43 | apurvanandan[m] | I am short on time for it
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| 15:43 | Bertl | fair enough, focus on the documentation
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| 16:23 | Bertl | off for now ... bbl
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| 20:23 | se6ast1an | off to bed, good night
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