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#apertus IRC Channel Logs

2019/07/21

Timezone: UTC


00:07
Spirit532
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04:25
Bertl
off to bed now ... have a good one everyone!
04:25
Bertl
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n0fx_[m]
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07:26
RexOrMatrix[m]
Greets.
07:41
BAndiT1983|away
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09:15
BAndiT1983
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09:15
BAndiT1983|away
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11:20
shebin_joseph
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11:21
shebin_joseph
Which is the best IDE for C++ ?
11:24
shebin_joseph
Visual Studio ?
11:28
shebin_joseph
?
11:33
shebin_joseph
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11:40
shebin_joseph
Anyone online ?
11:43
shebin_joseph71
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11:43
shebin_joseph71
Hello
11:44
shebin_joseph71
Is systemd can be used only in linux based OS ?
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d0x[m]
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shebin_joseph71
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11:59
shebin_joseph
Anyone online ?
11:59
shebin_joseph
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12:21
BAndiT1983
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12:57
aSobhy
hello Bertl I have a problem :
12:57
aSobhy
for the signal alignwd in the module CLKDIVC I'm raise it to '1' at the falling edge of s_clk and reset it after 1 cycle of e_clk that should make the s_clk = 5 e_clk
12:57
aSobhy
when I do that It works wrong :
12:57
aSobhy
for some cycles works correctly and the other cycles doesn't respond to it (alignwd signal).
12:57
aSobhy
I tried to simulate the file generated from lattice diamond for machxo2 devices it behave the same
12:57
aSobhy
what should i do ?!
13:04
niemand
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RexOrCine|away
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14:11
Kjetil
fix it ;) (I'm helping)
14:21
Bertl_zZ
changed nick to: Bertl
14:22
Bertl
morning folks!
14:22
apurvanandan[m]
Good morning Bertl
14:23
Bertl
aSobhy: the CLKDIVC primitive can only divide by 2, 3.5 or 4
14:28
aSobhy
morning Bertl
14:31
aSobhy
ok I'm dividing the eclk by 4 but when the alignwd is fired ('1') the sclk should increased by 1 cycle of e_clk for and that will happen only for the cycle of the alignwd is raised
14:38
Bertl
it is nice to see that you explore unusual pathes, but there is a problem here: we do not really know how ALIGNWD is implemented
14:38
Bertl
(you might find out via the simulation HDL though)
14:39
Bertl
all I found so far about ALIGNWD is that it can be async, but it needs to be 2 clock cycles wide
14:41
apurvanandan[m]
Hey aSobhy , you can see how I have used ALIGNWD: https://github.com/apurvanandan1997/BER_measurement/blob/master/MachXO2/Receiver/deserializer8_1.vhd#L146
14:41
apurvanandan[m]
It is working perfectly fine for me!
14:49
aSobhy
thats also what I found and didn't find any description for it else
14:50
BAndiT1983|away
changed nick to: BAndiT1983
14:50
aSobhy
It blows my mind really it works for some cycles and the other no
14:51
aSobhy
Ok apurvanandan[m] I'll check with you :)
14:56
shebin_joseph
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14:56
shebin_joseph
hello
14:57
Bertl
btw, when 'abusing' something like the word alignment of a clock divider, you need to double and triple check that it doesn't have any adverse effect on the result
14:57
Bertl
i.e. it might easily be that this adds constant jitter to the resulting clock signal
14:58
Bertl
a better way to would be a gated clock which is designed for things like this
14:58
shebin_joseph
is systemd can be installed only in linux based OS ?
14:59
Bertl
yup
14:59
shebin_joseph
actually,what is its use ?managing data in server ?
15:01
Bertl
https://en.wikipedia.org/wiki/Systemd
15:02
shebin_joseph
so should i install ubuntu or kali linux OS in my pc to install it ?
15:05
Bertl
we use Arch Linux on the Beta
15:10
shebin_joseph
is it easy to use...I am competely unware of linux ....only used windows in my whole life
15:15
BAndiT1983
https://lmgtfy.com/?q=how+easy+is+it+to+use+linux
15:27
aSobhy
OK Bertl I'll see gated clock and back again
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BAndiT1983
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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RexOrCine
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19:38
BAndiT1983
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20:09
se6astian
off to bed
20:09
se6astian
good night
20:09
se6astian
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20:09
Bertl
nn
20:59
apurvanandan[m]
Hey, I have succesfulyy added Clock domain crossing with a fifo and I am able to receive the words very accurately from the PRNG on the machXO2
21:01
apurvanandan[m]
But the previous problem still exist, the words from the Zynq/Virtex side get errored when they change ie constant words are correct
21:02
apurvanandan[m]
But it is very comfortable to debug with accurate data after the CDC
21:19
BAndiT1983|away
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21:31
Bertl
good!
21:32
Bertl
do you have some sample output from a change?
21:32
Bertl
i.e. what values do you get at what data rates?
21:32
apurvanandan[m]
Do you want exact values? ( paste here?)
21:33
Bertl
pastebin
21:33
Bertl
and yes, acutal values you receive
21:33
apurvanandan[m]
Great, just two minutes!
21:40
apurvanandan[m]
https://pastebin.com/TEEAMfqR Here it is
21:41
Bertl
okay, what am I seeing here?
21:41
apurvanandan[m]
You can ignore the decimal number here
21:41
Bertl
i.e. what are the columns?
21:41
apurvanandan[m]
It is decimal coversion of 32 bits
21:42
apurvanandan[m]
0 0 are unconnted currently
21:42
Bertl
hmm, why would you use decimal for 32bit?
21:42
apurvanandan[m]
Rightmost column is the PRNG on MachXO2
21:42
apurvanandan[m]
Sorry the counter on machXO2
21:42
Bertl
in truncated binary, right flushed?
21:42
apurvanandan[m]
second last column is word received from Virtex 5
21:43
apurvanandan[m]
Yes
21:43
apurvanandan[m]
I used decimal earlier, not currently in use
21:43
Bertl
and word is after decoding?
21:43
apurvanandan[m]
Yes
21:43
Bertl
so you are not getting a single correct value here as it looks?
21:44
apurvanandan[m]
So the two words sent are D19.6 = 11010011 and D5.5 = 10100101
21:44
Bertl
ah, okay
21:44
apurvanandan[m]
Approx 4-5 values I receive are correct
21:45
Bertl
what is the decimal value in the first number column again?
21:46
apurvanandan[m]
I am not sure but on digging right now I found that the encoded data received has errors, no sure though ( I saw '000111' many times which should occer with encoded 19.6 and 5.5)
21:46
apurvanandan[m]
shouldn't occur*
21:46
Bertl
okay, let's modify your test setup in the following way:
21:47
apurvanandan[m]
The decimal column is the decimal value of all cloums concatenated and then converted in decimal
21:47
apurvanandan[m]
It has no significance here
21:47
apurvanandan[m]
It can be ignored right now
21:48
Bertl
lol, why would you do that?
21:48
Bertl
anyway, so we expect 11010011 and 10100101 in alternating sequence, yes?
21:49
apurvanandan[m]
When I used 32-bit counter during FT601 controller testing :)
21:49
Bertl
how many of each do we expect?
21:49
apurvanandan[m]
No not in alternate but one 8 times then other 8 times
21:49
Bertl
note: in the future, use hex format for 2^N bit values
21:49
Bertl
and then?
21:50
apurvanandan[m]
Alternatively 8 times
21:50
Bertl
so eight of each, and then another cycle
21:50
apurvanandan[m]
Alternatively 8 times each
21:50
apurvanandan[m]
I mean AAAAAAAABBBBBBBB
21:50
Bertl
and this repeats I presume
21:51
apurvanandan[m]
Yes
21:51
apurvanandan[m]
I have joined it to 4rth bit of a counter
21:51
Bertl
and this is with the same datarate as your debug output
21:52
apurvanandan[m]
Actually there is gearing invovled for 60 to 100 conversion, should I tell what I did there?
21:52
apurvanandan[m]
60MHz to 100MHz
21:52
Bertl
well, do I want to know?
21:53
Bertl
anyway, the decoded value will not be of much help here
21:54
Bertl
so, here is a plan for better debugging:
21:54
Bertl
first, improve on the FIFO so that you do not need any clock conversion
21:55
Bertl
this is simple, just output bytes at 100MHz (FTDI clock) as long as there is data in the FIFO
21:55
Bertl
skip output when you do not have any data
21:55
Bertl
s/bytes/words/
21:56
Bertl
on the lower clock it's simple, just stuff data into the FIFO whenever you like
21:56
Bertl
for the debugging, we are mostly interested in the 10bit 'encoded' data
21:57
Bertl
so pick up the encoded data on the receiver and combine it with the decoded values and send that to the fifo
21:57
Bertl
note that the decoder will have a 'known' delay you want to compensate when combining the data
22:00
apurvanandan[m]
Ok , doing this. But for gearing I collected 6 bytes of 60MHz data sent to FIFO at 10 MHz then took the data out at 10MHz and spread the 6 bytes over 10 clock cyles of 100 MHz clock
22:00
apurvanandan[m]
replace bytes with 2 bytes
22:00
Bertl
not a good idea
22:01
Bertl
you cannot assume that your 60MHz are in sync with the 100MHz
22:01
Bertl
as a matter of fact, it is extremely unlikely they are
22:01
Bertl
so one clock will be faster than the other
22:02
Bertl
(after gearing)
22:02
apurvanandan[m]
Thats what I got after hours of thinking but ok I will change this. Will this work just for testing?
22:02
Bertl
if the 100MHz is running relatively faster than the 60MHz
22:02
Bertl
i.e. let's say it is 100.1 MHz
22:02
Bertl
and the 60Mhz is spot on
22:03
Bertl
then you will end up with an underrun sooner or later
22:03
Bertl
because the 100.1Mhz will transfer more data than the 60MHz produces
22:03
Bertl
if it is slightly slower, e.g. 99.9Mhz you will get an overrun
22:04
Bertl
because the data cannot be transferred 'as fast' as it is produced
22:04
Bertl
the solution here is the FIFO
22:04
Bertl
but you need to make sure that there is a way to cope with the over and underruns
22:05
apurvanandan[m]
I have taken care of overruns and underrun btw
22:05
Bertl
if you check the fifo fill state and only send data to the FTDI when it actually has data, you will handle the underrun
22:05
Bertl
and if you put less data into the FIFO than the other end is designed for, you get rid of the overrun
22:05
Bertl
so, if you produce data at 60MHz, just feed it into the FIFO
22:06
Bertl
because the 100MHz clock on the other end will take care of keeping it 'almost' empty
22:06
BAndiT1983
changed nick to: BAndiT1983|away
22:07
apurvanandan[m]
Ahhh, Definitely nice :)
22:08
apurvanandan[m]
And what should be FIFO depth and width?
22:08
Bertl
you want to transfer 32bit via the FTDI, yes?
22:09
Bertl
so the FIFO width should be 32bit then
22:09
apurvanandan[m]
Yes, but for five channels 8 bit we will need 40 bit
22:10
Bertl
start with two or one channel for now
22:10
apurvanandan[m]
And depth?
22:10
aSobhy
apurvanandan[m]: I need a favor please, after finishing with Bertl I'll tell you.
22:10
Bertl
but in any case, you want to have the width of the FTDI interface and do any gearing on the other end
22:11
Bertl
for the depth, with 60MHz on your generator side, at most 2 'words' will be in the FIFO at any time
22:11
Bertl
so minimal depth is perfectly fine, make it 4 or 8 to be on the safe side
22:12
Bertl
(or whatever fifo depth is available for 32bit)
22:12
apurvanandan[m]
Current depth x width = 512 x 96 XD
22:12
apurvanandan[m]
aSobhy: Ok coming
22:14
apurvanandan[m]
But I am first correcting the faulty data then I will do this FIFO task ( I have taken care of over and underrun)
23:29
Bertl
off to bed now ... have a good one everyone!
23:29
Bertl
changed nick to: Bertl_zZ