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Visual Studio ?

Anyone online ?

Hello

Anyone online ?

for the signal alignwd in the module CLKDIVC I'm raise it to '1' at the falling edge of s_clk and reset it after 1 cycle of e_clk that should make the s_clk = 5 e_clk

for some cycles works correctly and the other cycles doesn't respond to it (alignwd signal).

what should i do ?!

Good morning Bertl

morning Bertl

it is nice to see that you explore unusual pathes, but there is a problem here: we do not really know how ALIGNWD is implemented

all I found so far about ALIGNWD is that it can be async, but it needs to be 2 clock cycles wide

It is working perfectly fine for me!

Ok apurvanandan[m] I'll check with you :)

hello

i.e. it might easily be that this adds constant jitter to the resulting clock signal

is systemd can be installed only in linux based OS ?

actually,what is its use ?managing data in server ?

so should i install ubuntu or kali linux OS in my pc to install it ?

is it easy to use...I am competely unware of linux ....only used windows in my whole life

OK Bertl I'll see gated clock and back again

good night

nn

But the previous problem still exist, the words from the Zynq/Virtex side get errored when they change ie constant words are correct

do you have some sample output from a change?

Do you want exact values? ( paste here?)

and yes, acutal values you receive

https://pastebin.com/TEEAMfqR Here it is

You can ignore the decimal number here

It is decimal coversion of 32 bits

hmm, why would you use decimal for 32bit?

Sorry the counter on machXO2

second last column is word received from Virtex 5

I used decimal earlier, not currently in use

Yes

So the two words sent are D19.6 = 11010011 and D5.5 = 10100101

Approx 4-5 values I receive are correct

I am not sure but on digging right now I found that the encoded data received has errors, no sure though ( I saw '000111' many times which should occer with encoded 19.6 and 5.5)

okay, let's modify your test setup in the following way:

It has no significance here

lol, why would you do that?

When I used 32-bit counter during FT601 controller testing :)

No not in alternate but one 8 times then other 8 times

and then?

so eight of each, and then another cycle

I mean AAAAAAAABBBBBBBB

Yes

and this is with the same datarate as your debug output

60MHz to 100MHz

anyway, the decoded value will not be of much help here

first, improve on the FIFO so that you do not need any clock conversion

skip output when you do not have any data

on the lower clock it's simple, just stuff data into the FIFO whenever you like

so pick up the encoded data on the receiver and combine it with the decoded values and send that to the fifo

Ok , doing this. But for gearing I collected 6 bytes of 60MHz data sent to FIFO at 10 MHz then took the data out at 10MHz and spread the 6 bytes over 10 clock cyles of 100 MHz clock

not a good idea

as a matter of fact, it is extremely unlikely they are

(after gearing)

if the 100MHz is running relatively faster than the 60MHz

and the 60Mhz is spot on

because the 100.1Mhz will transfer more data than the 60MHz produces

because the data cannot be transferred 'as fast' as it is produced

but you need to make sure that there is a way to cope with the over and underruns

if you check the fifo fill state and only send data to the FTDI when it actually has data, you will handle the underrun

so, if you produce data at 60MHz, just feed it into the FIFO

And what should be FIFO depth and width?

so the FIFO width should be 32bit then

start with two or one channel for now

apurvanandan[m]: I need a favor please, after finishing with Bertl I'll tell you.

for the depth, with 60MHz on your generator side, at most 2 'words' will be in the FIFO at any time

(or whatever fifo depth is available for 32bit)

aSobhy: Ok coming

off to bed now ... have a good one everyone!