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#apertus IRC Channel Logs

2019/07/21

Timezone: UTC


01:07
Spirit532
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05:25
Bertl
off to bed now ... have a good one everyone!
05:25
Bertl
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n0fx_[m]
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08:26
RexOrMatrix[m]
Greets.
08:41
BAndiT1983|away
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10:15
BAndiT1983
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10:15
BAndiT1983|away
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12:20
shebin_joseph
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12:21
shebin_joseph
Which is the best IDE for C++ ?
12:24
shebin_joseph
Visual Studio ?
12:28
shebin_joseph
?
12:33
shebin_joseph
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12:40
shebin_joseph
Anyone online ?
12:43
shebin_joseph71
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12:43
shebin_joseph71
Hello
12:44
shebin_joseph71
Is systemd can be used only in linux based OS ?
12:46
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d0x[m]
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shebin_joseph71
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12:59
shebin_joseph
Anyone online ?
12:59
shebin_joseph
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13:21
BAndiT1983
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13:57
aSobhy
hello Bertl I have a problem :
13:57
aSobhy
for the signal alignwd in the module CLKDIVC I'm raise it to '1' at the falling edge of s_clk and reset it after 1 cycle of e_clk that should make the s_clk = 5 e_clk
13:57
aSobhy
when I do that It works wrong :
13:57
aSobhy
for some cycles works correctly and the other cycles doesn't respond to it (alignwd signal).
13:57
aSobhy
I tried to simulate the file generated from lattice diamond for machxo2 devices it behave the same
13:57
aSobhy
what should i do ?!
14:04
niemand
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14:15
RexOrCine|away
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15:11
Kjetil
fix it ;) (I'm helping)
15:21
Bertl_zZ
changed nick to: Bertl
15:22
Bertl
morning folks!
15:22
apurvanandan[m]
Good morning Bertl
15:23
Bertl
aSobhy: the CLKDIVC primitive can only divide by 2, 3.5 or 4
15:28
aSobhy
morning Bertl
15:31
aSobhy
ok I'm dividing the eclk by 4 but when the alignwd is fired ('1') the sclk should increased by 1 cycle of e_clk for and that will happen only for the cycle of the alignwd is raised
15:38
Bertl
it is nice to see that you explore unusual pathes, but there is a problem here: we do not really know how ALIGNWD is implemented
15:38
Bertl
(you might find out via the simulation HDL though)
15:39
Bertl
all I found so far about ALIGNWD is that it can be async, but it needs to be 2 clock cycles wide
15:41
apurvanandan[m]
Hey aSobhy , you can see how I have used ALIGNWD: https://github.com/apurvanandan1997/BER_measurement/blob/master/MachXO2/Receiver/deserializer8_1.vhd#L146
15:41
apurvanandan[m]
It is working perfectly fine for me!
15:49
aSobhy
thats also what I found and didn't find any description for it else
15:50
BAndiT1983|away
changed nick to: BAndiT1983
15:50
aSobhy
It blows my mind really it works for some cycles and the other no
15:51
aSobhy
Ok apurvanandan[m] I'll check with you :)
15:56
shebin_joseph
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15:56
shebin_joseph
hello
15:57
Bertl
btw, when 'abusing' something like the word alignment of a clock divider, you need to double and triple check that it doesn't have any adverse effect on the result
15:57
Bertl
i.e. it might easily be that this adds constant jitter to the resulting clock signal
15:58
Bertl
a better way to would be a gated clock which is designed for things like this
15:58
shebin_joseph
is systemd can be installed only in linux based OS ?
15:59
Bertl
yup
15:59
shebin_joseph
actually,what is its use ?managing data in server ?
16:01
Bertl
https://en.wikipedia.org/wiki/Systemd
16:02
shebin_joseph
so should i install ubuntu or kali linux OS in my pc to install it ?
16:05
Bertl
we use Arch Linux on the Beta
16:10
shebin_joseph
is it easy to use...I am competely unware of linux ....only used windows in my whole life
16:15
BAndiT1983
https://lmgtfy.com/?q=how+easy+is+it+to+use+linux
16:27
aSobhy
OK Bertl I'll see gated clock and back again
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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RexOrCine
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20:38
BAndiT1983
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21:09
se6astian
off to bed
21:09
se6astian
good night
21:09
se6astian
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21:09
Bertl
nn
21:59
apurvanandan[m]
Hey, I have succesfulyy added Clock domain crossing with a fifo and I am able to receive the words very accurately from the PRNG on the machXO2
22:01
apurvanandan[m]
But the previous problem still exist, the words from the Zynq/Virtex side get errored when they change ie constant words are correct
22:02
apurvanandan[m]
But it is very comfortable to debug with accurate data after the CDC
22:19
BAndiT1983|away
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22:31
Bertl
good!
22:32
Bertl
do you have some sample output from a change?
22:32
Bertl
i.e. what values do you get at what data rates?
22:32
apurvanandan[m]
Do you want exact values? ( paste here?)
22:33
Bertl
pastebin
22:33
Bertl
and yes, acutal values you receive
22:33
apurvanandan[m]
Great, just two minutes!
22:40
apurvanandan[m]
https://pastebin.com/TEEAMfqR Here it is
22:41
Bertl
okay, what am I seeing here?
22:41
apurvanandan[m]
You can ignore the decimal number here
22:41
Bertl
i.e. what are the columns?
22:41
apurvanandan[m]
It is decimal coversion of 32 bits
22:42
apurvanandan[m]
0 0 are unconnted currently
22:42
Bertl
hmm, why would you use decimal for 32bit?
22:42
apurvanandan[m]
Rightmost column is the PRNG on MachXO2
22:42
apurvanandan[m]
Sorry the counter on machXO2
22:42
Bertl
in truncated binary, right flushed?
22:42
apurvanandan[m]
second last column is word received from Virtex 5
22:43
apurvanandan[m]
Yes
22:43
apurvanandan[m]
I used decimal earlier, not currently in use
22:43
Bertl
and word is after decoding?
22:43
apurvanandan[m]
Yes
22:43
Bertl
so you are not getting a single correct value here as it looks?
22:44
apurvanandan[m]
So the two words sent are D19.6 = 11010011 and D5.5 = 10100101
22:44
Bertl
ah, okay
22:44
apurvanandan[m]
Approx 4-5 values I receive are correct
22:45
Bertl
what is the decimal value in the first number column again?
22:46
apurvanandan[m]
I am not sure but on digging right now I found that the encoded data received has errors, no sure though ( I saw '000111' many times which should occer with encoded 19.6 and 5.5)
22:46
apurvanandan[m]
shouldn't occur*
22:46
Bertl
okay, let's modify your test setup in the following way:
22:47
apurvanandan[m]
The decimal column is the decimal value of all cloums concatenated and then converted in decimal
22:47
apurvanandan[m]
It has no significance here
22:47
apurvanandan[m]
It can be ignored right now
22:48
Bertl
lol, why would you do that?
22:48
Bertl
anyway, so we expect 11010011 and 10100101 in alternating sequence, yes?
22:49
apurvanandan[m]
When I used 32-bit counter during FT601 controller testing :)
22:49
Bertl
how many of each do we expect?
22:49
apurvanandan[m]
No not in alternate but one 8 times then other 8 times
22:49
Bertl
note: in the future, use hex format for 2^N bit values
22:49
Bertl
and then?
22:50
apurvanandan[m]
Alternatively 8 times
22:50
Bertl
so eight of each, and then another cycle
22:50
apurvanandan[m]
Alternatively 8 times each
22:50
apurvanandan[m]
I mean AAAAAAAABBBBBBBB
22:50
Bertl
and this repeats I presume
22:51
apurvanandan[m]
Yes
22:51
apurvanandan[m]
I have joined it to 4rth bit of a counter
22:51
Bertl
and this is with the same datarate as your debug output
22:52
apurvanandan[m]
Actually there is gearing invovled for 60 to 100 conversion, should I tell what I did there?
22:52
apurvanandan[m]
60MHz to 100MHz
22:52
Bertl
well, do I want to know?
22:53
Bertl
anyway, the decoded value will not be of much help here
22:54
Bertl
so, here is a plan for better debugging:
22:54
Bertl
first, improve on the FIFO so that you do not need any clock conversion
22:55
Bertl
this is simple, just output bytes at 100MHz (FTDI clock) as long as there is data in the FIFO
22:55
Bertl
skip output when you do not have any data
22:55
Bertl
s/bytes/words/
22:56
Bertl
on the lower clock it's simple, just stuff data into the FIFO whenever you like
22:56
Bertl
for the debugging, we are mostly interested in the 10bit 'encoded' data
22:57
Bertl
so pick up the encoded data on the receiver and combine it with the decoded values and send that to the fifo
22:57
Bertl
note that the decoder will have a 'known' delay you want to compensate when combining the data
23:00
apurvanandan[m]
Ok , doing this. But for gearing I collected 6 bytes of 60MHz data sent to FIFO at 10 MHz then took the data out at 10MHz and spread the 6 bytes over 10 clock cyles of 100 MHz clock
23:00
apurvanandan[m]
replace bytes with 2 bytes
23:00
Bertl
not a good idea
23:01
Bertl
you cannot assume that your 60MHz are in sync with the 100MHz
23:01
Bertl
as a matter of fact, it is extremely unlikely they are
23:01
Bertl
so one clock will be faster than the other
23:02
Bertl
(after gearing)
23:02
apurvanandan[m]
Thats what I got after hours of thinking but ok I will change this. Will this work just for testing?
23:02
Bertl
if the 100MHz is running relatively faster than the 60MHz
23:02
Bertl
i.e. let's say it is 100.1 MHz
23:02
Bertl
and the 60Mhz is spot on
23:03
Bertl
then you will end up with an underrun sooner or later
23:03
Bertl
because the 100.1Mhz will transfer more data than the 60MHz produces
23:03
Bertl
if it is slightly slower, e.g. 99.9Mhz you will get an overrun
23:04
Bertl
because the data cannot be transferred 'as fast' as it is produced
23:04
Bertl
the solution here is the FIFO
23:04
Bertl
but you need to make sure that there is a way to cope with the over and underruns
23:05
apurvanandan[m]
I have taken care of overruns and underrun btw
23:05
Bertl
if you check the fifo fill state and only send data to the FTDI when it actually has data, you will handle the underrun
23:05
Bertl
and if you put less data into the FIFO than the other end is designed for, you get rid of the overrun
23:05
Bertl
so, if you produce data at 60MHz, just feed it into the FIFO
23:06
Bertl
because the 100MHz clock on the other end will take care of keeping it 'almost' empty
23:06
BAndiT1983
changed nick to: BAndiT1983|away
23:07
apurvanandan[m]
Ahhh, Definitely nice :)
23:08
apurvanandan[m]
And what should be FIFO depth and width?
23:08
Bertl
you want to transfer 32bit via the FTDI, yes?
23:09
Bertl
so the FIFO width should be 32bit then
23:09
apurvanandan[m]
Yes, but for five channels 8 bit we will need 40 bit
23:10
Bertl
start with two or one channel for now
23:10
apurvanandan[m]
And depth?
23:10
aSobhy
apurvanandan[m]: I need a favor please, after finishing with Bertl I'll tell you.
23:10
Bertl
but in any case, you want to have the width of the FTDI interface and do any gearing on the other end
23:11
Bertl
for the depth, with 60MHz on your generator side, at most 2 'words' will be in the FIFO at any time
23:11
Bertl
so minimal depth is perfectly fine, make it 4 or 8 to be on the safe side
23:12
Bertl
(or whatever fifo depth is available for 32bit)
23:12
apurvanandan[m]
Current depth x width = 512 x 96 XD
23:12
apurvanandan[m]
aSobhy: Ok coming
23:14
apurvanandan[m]
But I am first correcting the faulty data then I will do this FIFO task ( I have taken care of over and underrun)
00:29
Bertl
off to bed now ... have a good one everyone!
00:29
Bertl
changed nick to: Bertl_zZ