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#apertus IRC Channel Logs

2019/03/21

Timezone: UTC


00:04
futarisIRCcloud
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00:07
RexOrCine
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02:48
aSobhy
Bertl_oO: hello :)
02:48
aSobhy
I appologize for the long delay :)
02:55
aSobhy
I have changed the code and raised the speed but not reaching the required speed could you advice me :)
02:55
aSobhy
i reached a speed 200mhz on maxV fpga
03:04
aSobhy
Can you check my code , I sent the git link to your mail
05:12
parimal
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05:28
Bertl_oO
aSobhy: I'm almost off to bed now ... will check the code in detail later but you definitely want to fix spacing (especially around operators) as well as indentation and code style (make sure that it is consistent)
05:32
Bertl_oO
off to bed now ... have a good one everyone!
05:32
Bertl_oO
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06:05
aSobhy
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07:20
Y_G
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Y_G
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08:03
Y_G
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08:06
Y_G
Hi,wrt to T1121 "Extend Camera Control Daemon" which scripts are we talking about ?
08:07
Y_G
Also can someone point me to resources in reference to "Add further camera/image sensor parameters, besides currently implemented image sensor plain register configuration, digital and analog gain, like white balance, color matrix for output etc."
08:07
Y_G
Thanks :)
08:21
se6astian|away
changed nick to: se6astian
08:23
se6astian
Y_G: here is the image sensor datasheet: https://github.com/apertus-open-source-cinema/beta-hardware/blob/master/Datasheets/datasheet_cmv12000_v2.11.pdf
08:23
se6astian
read up on the registers and sensor parameters
09:11
bermax_bxl
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09:11
bermax_bxl
hello everyone !
09:29
Y_G
Thanks se6astian :)
09:29
Y_G
Any pointers on the first question ?
09:47
se6astian
no sorry
10:04
Y_G
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10:28
se6astian
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10:44
anuejn
the scripts are located in here: https://github.com/apertus-open-source-cinema/axiom-beta-firmware/tree/master/software/scripts
11:25
vup2
the most interesting of the scripts is probably start.sh and the various sub-scripts it calls / uses
11:39
Bertl_zZ
changed nick to: Bertl
11:39
Bertl
morning folks!
11:51
se6astian|away
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12:32
aSobhy
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12:34
aSobhy
well i have formatted the signal names and spacing , is the code still unclear ?
12:36
Bertl
it's not that I have a problem reading ugly (badly formatted) code, it's just that it hurts my eyes :)
12:36
Bertl
so let's see if you did a good job in not hurting my eyes ...
12:38
Bertl
nope ... okay let's go through the code and see where you could improve on formatting
12:39
Bertl
first, if possible, try to stay within 80 characters width
12:39
Bertl
comments can hang out if necessary, but it usually is a sign that you want to adjust something ...
12:40
Bertl
then, stick to a specific indentation width ... 8 or 4 characters typically, but do not switch
12:40
Bertl
looking at ser2par.vhd now
12:41
Bertl
you start with 8 char indentations in line 5 and keep that in line 8
12:41
Bertl
but in line 23/24 you are down to 4 characters
12:41
Bertl
(note that 4 chars is probably a lot better as you have wide lines)
12:42
Bertl
in line five, the generic, is camelCase while in line 12 the input is using underscores
12:43
Bertl
you want to stick to underscores, camelCase is for C++
12:43
Bertl
hint: generics are better written all upper case (like constants) so you can easily tell them from signals or variables
12:44
Bertl
line 10, you have 'serialBit :in' in line 11 you have 'bitslip: in' both should use a space on the left and right of the ':'
12:45
Bertl
this continues throughout the entire file
12:45
Bertl
line 30, you have 'end component ;' which should be 'end component;'
12:46
Bertl
in line 12 you use 'std_logic_vector (1 downto 0);' (which IMHO is good) but in line 40 you have 'std_logic_vector(size-1 downto 0);' (note the missing space)
12:47
Bertl
line 73 has an additional space before the ')' which shouldn't be there
12:48
Bertl
there is also lots of empty lines without meaning (space for notes?)
12:48
Bertl
note: it's okay to use a single or double empty line to separate blocks, but there should be a good reason for 3+ empty lines
12:49
Bertl
(and there is no reason for empty lines at the end :)
12:49
Bertl
line 93, '(size=> 8)' is missing a space before the operator
12:50
Bertl
line 108 has an additional space before the ';'
12:52
Bertl
of course those are only examples of bad formatting, basically every second line is badly formatted ...
12:59
Bertl
now for the question why it isn't as fast as you expect it to be
13:01
Bertl
there are a number of logic operations which most likely have a larger depth than one lut (check with the tools for details) so you might want to look into that and if you find such pathes in the list of critical ones, you want to consider pipelining those
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parimal
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BAndiT1983|away
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16:52
Bertl
off for now ... bbl
16:52
Bertl
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BAndiT1983
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17:30
se6astian
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BAndiT1983|away
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Spirit532
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18:38
aSobhy
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18:39
aSobhy
i will do that and update the code :) thanks alot
18:42
aSobhy
but i have divided the combination gates by a register to be : reg -> 1 component (eg . 3 input AND) -> reg and so on
18:45
aSobhy
another question : is it accepted to have the parallel data (output) delayed one cycle than it should be ?
18:53
se6astian|away
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19:23
niemand
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niemand
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niemand
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20:29
aSobhy
i have done those modification to the code and update it :)
20:55
Bertl_oO
aSobhy: there is no problem with delays on the parallel side
20:56
Bertl_oO
after all, there is already a delay due to the transfer
20:56
Bertl_oO
so as long as you know how much the delay is, it will be fine
21:00
aSobhy
ok, i will try another idea and talk to you again :)
21:01
aSobhy
i hope it will pass , thanks Bertl :D
21:03
Bertl_oO
will check the code for formatting a little later and give some feedback
21:09
aSobhy
ok I would be grateful :)
21:11
Bertl_oO
btw, VHDL 2019 is out, so most tools by now support VHDL 2008 *G*
21:12
Bertl_oO
(just saying, because it simplifies things a lot)
21:16
futarisIRCcloud
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21:19
aSobhy
OK, I'll see for the difference :D
21:20
Bertl_oO
note: you have to enable it on most tools though (VHDL 2008) and usually not all features are supported (you have to check)
21:23
aSobhy
OK
21:23
niemand
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21:50
se6astian
good night
21:50
Bertl_oO
nn
21:51
se6astian
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23:48
aSobhy
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