#apertus IRC Channel Logs

@FergusL I think he's referring to switching barriers

Oops, this is gwelkind, let me log in derp derp derp

there we go, yeah, sorry I was trying to solder a PIC board, barely looking at my computer

hahah, yeah, it went really poorly

Every polar capacitor anyways

Dunno, I couldn't see a thing through the waves of vaporous tin smog

I assumed that cathode was the positive end, because cations are positively charged!

and simply don't use polarized capacitors unless you really need to (for typical microcontrollers, you usually don't)

yeh sebastian told me to talk to you about hardware stuff and in what ways i can contribute to the project

(and most importantly, what would you like to talk about :)

okay, I read that you have some experience there, did you get a chance to have a look at the FE design yet?

I've had a look at the existing EagleCAD files for the prototype board

so what's your comment on that so far? any obvious issues, potential problems, improvements?

correct

i'm surprised you didn't need to length match all the LVDS pairs... and purely relying on the FPGA adjustable IODELAYS

do you know the LVDS frequency?

i think there was a new version of the CMV12000 recently

correct, we are at 300MHz LVDS clock

for my project we used the CMV2000 and i recall it could go up to 480mbits/sec

wow!!!

or more?

yep, do you have an idea how long 300MHz are wavelength wise?

300 mhz........around 3 ns period

:P

yeah, it's about half the length in copper

10% of the wavelength?

but the more the better (from a timing perspective) right? the more margin you have without need to use IODELAYS for tuning

http://vserver.13thfloor.at/Stuff/AXIOM/LVDS_netlen.txt

ahh right

(a lot of work :P)

what does that give with roughly 250mm wavelength?

so while I could have trimmed them to match more closely, the gain would be questionable

what is it?

so I'd suspect a pattern which closely matches the total wire lengths

sorry, late here

but that's what I get instead

so I presume the synthesis tools add a systematic delay which I haven't figured out yet

has its pairs matched?

the FMC specification requires good matching

and I checked with the net length on the zedboard as well

I also looked at the beforementioned package differences, although they are a magnitude smaller

so I presume it is an artificial delay the tools add for whatever reason

that is strange

i.e. the FE lengths, the zedboard lengths and the package lengths

could be

sebastian told me a little bit about the non-prototype axiom

probably the best source of information for the beta prototype (the next step) are the IRC logs

basically we figured that something like the Zynq comes handy

which limits it to the 7030 and the newest member the 7015

we want to have between 0.5 and 1GB of memory to handle the data, we would like to see some of it on the FPGA side

(so you are running in open doors here if you suggest to use kikad :)

what does it mean?

"to kick at an open door"

the reason I chose eagle was that I've been using it for quite some time, and I wanted to complete the frontend quickly ... and I tested beforehand that I can convert most of the eagle layout and schematic to kicad later

a second argument pro eagle was the fact that OSHpark processes eagle files directly

i am presuming you're going to do the beta prototype PCB's as well

of course, open source software is always preferred, but 'open' document formats are good enough

haha

I'm hoping that the CERN involvement in kicad will speed up development significantly

last time I checked, I had some troubles working with the router (not autorouter) and mostly visual issues

(I was able to fix a few things with patches though :)

also back/forward annotation was not working as expected

looking at the CERN page I see python scripting, which sounds good :)

haven't used that in kicad

i installed it two years ago

then crawled back to non-open source tools

I see, so what do you use atm?

i mostly 90% use altium

so, do you know how to properly export a schematic/layout in altium so that it can be used e.g. in kicad or eagle?

I see ... what did you pay for your altium package?

and now I use Altium at work...

so the company you're working for pays that for you

so all the work projects are done in Altium

I see

nope :)

did you design the elphel cameras?

when do you plan for the beta prototype PCB design to start happening?

what are you working on at the moment?

is the current focus to get good images and videos from the alpha prototype for the purposes of crowdfunding?

and of course, we want to get an idea if the chosen path is the right one

goodnight!

Hi there

morning sir !

I everyone