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04:14 | Guest6616 | @FergusL I think he's referring to switching barriers
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04:14 | Guest6616 | http://en.wikipedia.org/wiki/Switching_barriers
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04:15 | Guest6616 | Oops, this is gwelkind, let me log in derp derp derp
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04:15 | Guest6616 | changed nick to: gwelkind
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04:17 | gwelkind | there we go, yeah, sorry I was trying to solder a PIC board, barely looking at my computer
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04:32 | Bertl | 'trying' doesn't sound promising :)
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04:53 | gwelkind | hahah, yeah, it went really poorly
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04:54 | gwelkind | I soldered on the LEDs and every capacitor backwards
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04:54 | gwelkind | Every polar capacitor anyways
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04:54 | carsonau | did you manage to get any magic blue smoke? :)
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04:55 | gwelkind | Dunno, I couldn't see a thing through the waves of vaporous tin smog
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04:55 | gwelkind | My lungs feel armor plated :P
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04:55 | gwelkind | I assumed that cathode was the positive end, because cations are positively charged!
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05:03 | Bertl | hmm, if you see tin smog, your temperatures are way to high :)
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05:04 | Bertl | and simply don't use polarized capacitors unless you really need to (for typical microcontrollers, you usually don't)
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05:05 | Bertl | carsonau: hey, IIRC you wanted to talk to me recently?
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05:05 | carsonau | yeh sebastian told me to talk to you about hardware stuff and in what ways i can contribute to the project
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05:06 | Bertl | great! so what is your main interest and where would you like to help?
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05:06 | Bertl | (and most importantly, what would you like to talk about :)
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05:07 | carsonau | i think i'll be most valuable in schematics / circuit design
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05:07 | Bertl | okay, I read that you have some experience there, did you get a chance to have a look at the FE design yet?
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05:07 | carsonau | what's the FE design?
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05:08 | carsonau | I've had a look at the existing EagleCAD files for the prototype board
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05:08 | Bertl | the sensor frontend we are using in the alpha prototype, yes
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05:08 | Bertl | so what's your comment on that so far? any obvious issues, potential problems, improvements?
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05:09 | carsonau | you designed that one right?
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05:09 | Bertl | correct
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05:10 | Bertl | but please, do not hold back
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05:10 | carsonau | i'm surprised you didn't need to length match all the LVDS pairs... and purely relying on the FPGA adjustable IODELAYS
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05:11 | Bertl | interesting that you mention that ...
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05:11 | Bertl | do you know the LVDS frequency?
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05:12 | carsonau | was it 300 mbits/sec for the CMV12000?
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05:12 | carsonau | i think there was a new version of the CMV12000 recently
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05:12 | carsonau | that could do higher?
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05:12 | Bertl | correct, we are at 300MHz LVDS clock
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05:12 | carsonau | for my project we used the CMV2000 and i recall it could go up to 480mbits/sec
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05:12 | Bertl | the more recent versions can do 600MHz
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05:12 | carsonau | wow!!!
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05:12 | carsonau | 32 LVDS channels?
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05:12 | carsonau | or more?
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05:13 | carsonau | 64?
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05:13 | Bertl | yep, do you have an idea how long 300MHz are wavelength wise?
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05:13 | Bertl | i.e. 32 channels atm, 64 max
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05:13 | carsonau | 300 mhz........around 3 ns period
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05:13 | carsonau | 45cm?
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05:13 | carsonau | :P
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05:13 | carsonau | rough estimate
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05:13 | Bertl | yeah, it's about half the length in copper
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05:14 | Bertl | so, what matching between different pairs would you suggest for good timing?
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05:14 | Bertl | 10% of the wavelength?
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05:16 | carsonau | 10% sounds reasonable
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05:16 | carsonau | but the more the better (from a timing perspective) right? the more margin you have without need to use IODELAYS for tuning
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05:17 | Bertl | in theory yes, although anything below 1% is probably useless, especially as there are package differences and similar
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05:17 | Bertl | http://vserver.13thfloor.at/Stuff/AXIOM/LVDS_netlen.txt
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05:17 | Bertl | here are the pair lengths in mm (on the frontend)
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05:17 | carsonau | ahh right
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05:18 | carsonau | you can account for the package differences as well! :)
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05:18 | carsonau | (a lot of work :P)
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05:18 | Bertl | so we roughly have 24mm max and 8mm min
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05:18 | Bertl | what does that give with roughly 250mm wavelength?
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05:19 | carsonau | i see
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05:19 | Bertl | so while I could have trimmed them to match more closely, the gain would be questionable
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05:20 | Bertl | but an interesting detail is that there is a really weird delay I attribute to the FPGA
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05:20 | carsonau | what is it?
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05:21 | Bertl | i.e. all LVDS channels are adjusted with the configurable INPUT delay elements
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05:22 | Bertl | so I'd suspect a pattern which closely matches the total wire lengths
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05:22 | Bertl | s/suspect/expect/
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05:22 | Bertl | sorry, late here
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05:23 | Bertl | http://vserver.13thfloor.at/Stuff/AXIOM/cmv_train2.out
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05:23 | Bertl | but that's what I get instead
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05:24 | Bertl | note that the LVDS channels are connected in a completely different way and that the configured delays do not match with the wire lengths either
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05:25 | Bertl | so I presume the synthesis tools add a systematic delay which I haven't figured out yet
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05:26 | carsonau | do you know if the zedboard
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05:27 | carsonau | has its pairs matched?
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05:27 | carsonau | or is your LVDS_netlen.txt
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05:27 | Bertl | the FMC specification requires good matching
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05:27 | carsonau | ahh right
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05:27 | Bertl | and I checked with the net length on the zedboard as well
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05:27 | carsonau | what about the bond wire flight times in the FPGA package?
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05:27 | Bertl | I also looked at the beforementioned package differences, although they are a magnitude smaller
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05:28 | carsonau | ahh right
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05:28 | Bertl | so I presume it is an artificial delay the tools add for whatever reason
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05:28 | Bertl | I have to write that together in a meaninfull way and ask our contact at xilinx about that
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05:29 | carsonau | that is strange
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05:29 | Bertl | but if you find that interesting, you might want to help putting together the various lengths from all involved parts
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05:29 | Bertl | i.e. the FE lengths, the zedboard lengths and the package lengths
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05:30 | Bertl | another interesting interpretation might be that the sensor produces those delays
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05:30 | carsonau | could be
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05:30 | Bertl | i.e. that the LVDS channels are not in sync as the documentation suggests
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05:31 | carsonau | sebastian told me a little bit about the non-prototype axiom
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05:31 | carsonau | is there a page on the wiki where i could read more about your plans for that?
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05:32 | Bertl | probably the best source of information for the beta prototype (the next step) are the IRC logs
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05:32 | carsonau | haha
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05:32 | Bertl | basically we figured that something like the Zynq comes handy
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05:33 | Bertl | we also figured that we probably want multi gigabit tranceivers
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05:33 | Bertl | which limits it to the 7030 and the newest member the 7015
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05:34 | carsonau | have you decided whether or not to use KiCAD for the beta?
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05:34 | Bertl | we want to have between 0.5 and 1GB of memory to handle the data, we would like to see some of it on the FPGA side
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05:34 | Bertl | we definitely would like to go with kikad if possible, really depends on who does the design
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05:35 | Bertl | (so you are running in open doors here if you suggest to use kikad :)
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05:35 | carsonau | sorry i'm not familiar with the expression "running in open doors" :P
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05:36 | carsonau | what does it mean?
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05:36 | Bertl | yeah, that is probably a bad translation, sec
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05:37 | Bertl | "to kick at an open door"
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05:38 | Bertl | does that make more sense to you? I.e. you do not need to convince me of kicad
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05:39 | Bertl | the reason I chose eagle was that I've been using it for quite some time, and I wanted to complete the frontend quickly ... and I tested beforehand that I can convert most of the eagle layout and schematic to kicad later
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05:39 | carsonau | oh ok
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05:40 | Bertl | a second argument pro eagle was the fact that OSHpark processes eagle files directly
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05:40 | Bertl | i.e. there is no need to break it down to gerbers
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05:40 | carsonau | i am presuming you're going to do the beta prototype PCB's as well
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05:42 | Bertl | I'm not sure, if there is a chance that we find somebody (person, team, partner) which is interested and willing to create the next prototype step with us, we are open in this regard
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05:42 | Bertl | of course, open source software is always preferred, but 'open' document formats are good enough
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05:43 | Bertl | for example, it's a real PITA to convert anything from Altium
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05:43 | carsonau | haha
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05:43 | Bertl | but since eagle switched to XML style documents, it is quite simple/easy to work with them
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05:44 | Bertl | I'm hoping that the CERN involvement in kicad will speed up development significantly
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05:44 | carsonau | what improvements would you like in KiCAD at the moment?
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05:45 | Bertl | last time I checked, I had some troubles working with the router (not autorouter) and mostly visual issues
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05:45 | Bertl | i.e. displeasing presentation, jerky scrolling/zooming, etc
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05:46 | Bertl | (I was able to fix a few things with patches though :)
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05:47 | Bertl | a nice eagle 'feature' are ULPs, and I haven't figure how/if kicad allows for something like that
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05:47 | Bertl | also back/forward annotation was not working as expected
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05:47 | Bertl | but that was last summer, so a lot might have been improved already
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05:49 | Bertl | looking at the CERN page I see python scripting, which sounds good :)
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05:52 | Bertl | btw, have you seen the P&S router in action? that's one of the most interesting features for me atm
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05:53 | carsonau | haven't used that in kicad
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05:53 | carsonau | in fact haven't used kicad much at all
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05:53 | carsonau | i installed it two years ago
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05:53 | carsonau | got fed up with using it
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05:53 | carsonau | then crawled back to non-open source tools
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05:53 | carsonau | haha
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05:54 | Bertl | I see, so what do you use atm?
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05:54 | Bertl | http://www.youtube.com/watch?v=zxHDAHpR5Ls (P&S)
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05:55 | carsonau | i mostly 90% use altium
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05:55 | carsonau | 10% eagle
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05:56 | Bertl | so, do you know how to properly export a schematic/layout in altium so that it can be used e.g. in kicad or eagle?
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05:56 | carsonau | never had the need to...so i do not know :(
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05:58 | Bertl | I see ... what did you pay for your altium package?
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05:59 | carsonau | during university, was in a solar car team, and Altium sponsored us licences...
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05:59 | carsonau | and now I use Altium at work...
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05:59 | carsonau | so I've never had to pay personally for Altium
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05:59 | Bertl | so the company you're working for pays that for you
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06:00 | carsonau | the company has the Altium licence
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06:00 | carsonau | so all the work projects are done in Altium
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06:00 | carsonau | I use Eagle for my personal projects
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06:00 | Bertl | I see
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06:00 | Bertl | anyway, back to the prototype ... anything else but the wire lengths?
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06:01 | carsonau | nope :)
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06:04 | carsonau | all looks good
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06:06 | carsonau | did you design the elphel cameras?
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06:07 | Bertl | nope, not involved at all
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06:09 | carsonau | when do you plan for the beta prototype PCB design to start happening?
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06:10 | Bertl | as soon as we finish the crowd funding
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06:11 | carsonau | what are you working on at the moment?
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06:12 | Bertl | noise compensation and FPGA image processing
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06:12 | carsonau | is the current focus to get good images and videos from the alpha prototype for the purposes of crowdfunding?
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06:12 | Bertl | correct
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06:13 | Bertl | and of course, we want to get an idea if the chosen path is the right one
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07:01 | Bertl | off to bed now ... have a good one everyone!
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07:01 | cksa | goodnight!
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11:07 | FergusL | Hi there
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11:13 | philippej | Hi FergusL
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16:26 | Bertl | morning everyone!
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16:30 | philippej | morning sir !
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17:00 | se6astian | good evening
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17:52 | opusprod | I everyone
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17:54 | Bertl | welcome opusprod!
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22:48 | se6astian | good night
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