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#apertus IRC Channel Logs

2017/12/20

Timezone: UTC


23:03
BAndiT1983
changed nick to: BAndiT1983|away
00:04
rton
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02:58
arpu
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arpu
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04:42
Bertl_oO
changed nick to: Bertl_zZ
06:47
se6astian|away
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06:54
seku_
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niemand
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niemand
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07:49
BAndiT1983|away
changed nick to: BAndiT1983
08:20
seku_
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sebix
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sebix
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sebix
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seku_
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seku_
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se6astian
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10:47
seku_
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12:34
rton
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13:06
se6astian|away
changed nick to: se6astian
14:43
seku_
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14:45
jarhab[m]
Bertl: What is the current plan for changing the bitstream of the FPGA, when the modules change?
14:46
jarhab[m]
reprogram the whole device or do some kind of partial reconfiguration?
14:47
jarhab[m]
and what is the current plan for doing it from the vhdl side? is there some kind of abstraction for image sensors and plugin modules?
14:48
se6astian
I think the current plan is to create a full new bitstream
14:48
pusle
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14:49
se6astian
but in the future (not sure if its ready) do particial reconfiguration
14:49
se6astian
*partial
14:50
pusle
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14:51
jarhab[m]
ok
14:52
jarhab[m]
so the plan is to have a simple "detection" bitstream, that reports the hardware that is installed to the os and then load the corresponding bitstream?
15:04
BAndiT1983
changed nick to: BAndiT1983|away
15:48
Bertl_zZ
changed nick to: Bertl_oO
15:48
Bertl_oO
changed nick to: Bertl
15:48
Bertl
morning folks!
15:51
BAndiT1983|away
changed nick to: BAndiT1983
15:51
Bertl
jarhab[m]: partial reconfiguration is the long term plan
16:05
sebix
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16:10
jarhab[m]
ah cool
16:10
jarhab[m]
but the interface isnt in place yet?
16:11
Bertl
nope, we are still using the Axiom Alpha firmware just heavily modified
17:02
se6astian
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17:03
niemand
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17:04
se6astian|away
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17:07
se6astian
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18:04
jarhab[m]
ok
18:27
danieeel
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18:44
seku
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18:45
Bertl
off for now ... bbl
18:45
Bertl
changed nick to: Bertl_oO
18:54
se6astian|away
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19:23
davidak
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pusle
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davidak
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21:00
se6astian
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rton
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niemand
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22:28
BAndiT1983
changed nick to: BAndiT1983|away