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#apertus IRC Channel Logs

2020/11/20

Timezone: UTC


00:31
mumptai
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RexOrCine
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BAndiT1983|away
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aombk2
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aombk
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07:05
Bertl_oO
off to bed now ... have a good one everyone!
07:05
Bertl_oO
changed nick to: Bertl_zZ
07:52
se6ast1an
good day
07:57
mumptai
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09:07
anuejn
good morning
09:21
comradekingu
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BAndiT1983
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10:33
BAndiT1983|away
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11:58
anuejn
Bertl_zZ: I have another problem where I need help:
11:58
anuejn
I cant get the pll to lock on a clock I am generating in the zynq
11:59
anuejn
I try to convert 50Mhz coming out of the zynq to 200Mhz
12:00
anuejn
the same pll configuration does lock when i feed it 50Mhz from the ft601
12:00
anuejn
however I can measure (with a counter) that both clock domains are really having 50Mhz
12:01
anuejn
so I suspect that there is some jitter related issue there
12:01
anuejn
do you have any ideas where this is coming from or how to debug that?
12:36
BAndiT1983
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BAndiT1983|away
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13:11
mumptai
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15:33
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mumptai
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15:53
Bertl_zZ
changed nick to: Bertl
15:53
Bertl
morning folks!
15:54
Bertl
anuejn: hmm, the MMC/PLL is usually quite good at syncing up to a signal even if it has a lot of jitter ...
15:54
Bertl
care to share some details about the setup?
16:01
anuejn
ah hm I mean the pll of the machxo2
16:01
anuejn
so my setup is:
16:02
anuejn
The usb3 plugin module plugged into the axiom micro
16:02
anuejn
on the micro I have a bitstream loaded that outputs a 50Mhz differential clock on lvds5 of the plugin module slot
16:03
anuejn
(that bank is jupered to vccio=2V5)
16:03
anuejn
(and the clock output is set as LVDS_25)
16:04
anuejn
the plugin module has that pair configured as input with iostandard LVDS25
16:06
anuejn
the differential input is fed (more or less) directly into CLKI of the EHXPLLJ primitive
16:06
anuejn
i am using CLKOP as the feedback path of the pll
16:07
anuejn
all dividers of the pll are set to 1 except for CLKFB_DIV which is set to 4
16:08
Bertl
is the signal properly terminated?
16:11
anuejn
no they are not!
16:11
anuejn
thanks for the idea
16:11
anuejn
will try that
16:11
anuejn
sadly the machxo only supports 100Ohm termination
16:11
anuejn
while I think we routed for 50Ohm?
16:16
Bertl
LVDS has 100 Ohm differential, so the plugin side should be fine there
16:18
Bertl
I don't know what you used on the micro though
16:18
anuejn
ah okay
16:18
Bertl
anyway, even if your traces are 50 Ohm differential, you will get way better results with termination than without :)
16:19
anuejn
I see
16:19
anuejn
however the pll still does not lock (with internal 100Ohm termination)
16:21
anuejn
and now I cant measure the 50Mhz with my counter anymore
16:21
Bertl
counter means?
16:22
anuejn
I have a counter driven by that clock
16:22
anuejn
which I can read out to verify my clocks
16:22
Bertl
HDL inside the MachXO2 I presume?
16:22
anuejn
and that counter is not counting up anymore
16:23
anuejn
yup
16:23
Bertl
okay, so that means that the signal is way to weak (termination killed it) or not really differential (only one trace is connected)
16:24
anuejn
sounds a bit like that lane is not really connected but wus just coupled in somehohw
16:24
Bertl
and the fact that it 'worked' before was more by accident than by design
16:25
anuejn
sounds convincing
16:25
Bertl
so my suggestion would be, get a scope (50MHz is not that much) and check the connector without plugin
16:25
Bertl
verify voltage levels on each signal of the LVDS pair
16:26
anuejn
measured from ground to that pin?
16:26
Bertl
yes
16:26
Bertl
you should measure a bias voltage (DC offset) and a swing (mix to max)
16:27
Bertl
signal should look almost identical on both pins, except that one goes up when the other goes down
16:27
Bertl
(you can measure them one after the other of course)
16:30
anuejn
on both pins i am measuring about 1.2V mean and 930mV peak to peak
16:31
anuejn
I have currently only one probe at hand so I cant check if they are really differential but i assume that works
16:32
anuejn
but overall the signal looks quite okay (i cant really judge as the scope i am looking at has only 60Mhz bw)
16:36
anuejn
with the plugin module plugged in i see around 500mv peak-to-peak on one pin and 1V peak-to-peak on the other
16:37
Bertl
that is suspicious :)
16:37
Bertl
i.e. it looks like it is only terminated on one side
16:38
Bertl
check that you have differential termination active
16:39
anuejn
ah hm... nmigen generated the io constraint only for the positive side
16:39
anuejn
that is... bad
16:46
anuejn
after fixing that the clock seems to change its amplitude with a rate of ~1Hz
16:47
anuejn
between roughly 500mV ptp and 1V ptp
16:47
anuejn
things are getting... more wired
16:55
anuejn
Bertl: any idea?
16:58
anuejn
hm... when I touch the plugin module and bend it a tiny bit to the left or right i can make that phenomenon appear / disappear
16:58
anuejn
the counter now counts again but the pll still doesnt lock
17:06
anuejn
hm... that seemed to be artifacts of the data i was transmitting on the other lanes
17:06
anuejn
maybe the plugin module has bad contact in the pcie slot or something like that
17:14
Bertl
sounds like a contact problem
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mumptai
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mumptai
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17:19
BAndiT1983
https://www.baconsports.com/wp-content/uploads/2013/09/blowing-into-nintendo-cartridge.jpg
17:20
Bertl
it's good to have an expert around :)
17:20
BAndiT1983
telling the same it crowd sentence lost it's point, so trying new things ;)
17:45
anuejn
when i plug it into the other plugin module slot the signal looks extremely crude and has only 300mv ptp
17:49
se6ast1an
ordered 4 sata3 ssds for bertl to test the SATA plugin module gateware from florent
17:49
Bertl
well, 300mV is a little on the low side, 400-500mV is more what I'd expect
17:55
anuejn
I dont know at all what i am doing here
17:55
anuejn
I think i give up for today
18:10
Bertl
so early? :)
19:05
BAndiT1983
Bertl: your day != day of mere mortal
19:09
Bertl
well, yeah, but at least since the invention of electrical light, folks stopped calling it a day when the sun goes down ....
19:19
BAndiT1983
:)
19:29
Bertl
off for now ... bbl
19:29
Bertl
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BAndiT1983
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