Current Server Time: 12:14 (Central Europe)

#apertus IRC Channel Logs

2020/07/20

Timezone: UTC


06:24
BAndiT1983|away
changed nick to: BAndiT1983
07:23
BAndiT1983
panintended: any day is okay
07:57
se6ast1an
what about today?
08:27
se6ast1an
I am waiting for an IKEA delivery between 9:00 - 13:00
08:33
BAndiT1983
should work
08:33
BAndiT1983
changed nick to: BAndiT1983|away
08:34
BAndiT1983|away
changed nick to: BAndiT1983
09:44
Bertl_oO
off to bed now ... have a good one everyone!
09:44
Bertl_oO
changed nick to: Bertl_zZ
09:53
pratyush
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pratyush
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10:09
mumptai
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10:23
MichaelSchwarzma
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10:35
se6ast1an
BAndiT1983: panintended so in 25 minutes or in 1h25?
10:35
panintended
Hi all
10:37
panintended
se6ast1an BAndiT1983 can we have it tomorrow or Wednesday 12:00 noontime UTC+2 time?
10:37
se6ast1an
I am at the university then but should work still
10:40
panintended
We can agree on another time as well. It's fine by me so long as I plan it. Another possibility would be today 17:00-18:00 UTC+2 for example.
10:40
panintended
I'd like to brush up on stuff related to the meeting so that I'm prepared and we can keep the meeting short and efficient for everyone.
10:40
panintended
What items will we discuss by the way?
10:45
BAndiT1983
no problem from my side, am working usually and won't leave at that time
10:46
BAndiT1983
am a bit out of the firmware topic, so would have also to check what's on the list, was looking more into BL-related stuff lately, but also occupied by other things a lot
10:50
se6ast1an
today before or after the IRC meeting is fine as well
10:50
se6ast1an
main topic would be remote firmware and observer pattern remaining todos, next steps
10:57
BAndiT1983
ok, i should be back till the meeting, will leave for an appointment after work
11:03
se6ast1an
panintended: please choose :)
11:05
panintended
Ok, let's go with 17:00-18:00 utc+2 time today if it's ok with everyone
11:09
BAndiT1983
won't work for me, as the appointment is at 16:00, don't know if i will back by then, but you both can discuss stuff and i can read and comment the logs later
11:12
se6ast1an
and tomorrow noon?
11:24
BAndiT1983
every noon while from monday to friday is ok for me
11:24
se6ast1an
then lets do tomorrow around noon7
11:25
se6ast1an
?
11:31
panintended
Yes, fine by me!
11:31
panintended
Tomorrow 12:00 UTC+2
11:46
se6ast1an
can we do 13:00 utc+2 so I can go to lunch with my university colleagues?
12:00
BAndiT1983
should be possible
12:07
se6ast1an
appointment noted
12:08
se6ast1an
also ok fr you panintended?
12:08
se6ast1an
*for
12:09
panintended
Yes, ok for me too
12:09
se6ast1an
great, noted
13:38
se6ast1an
first cp enclosure fan test results are in: https://paste.pics/9LTS7
13:39
se6ast1an
just spotted one wrong marker though :)
13:43
se6ast1an
conclusion: just a small amount of airflow works to keep everything well within the healthy operation temperature range
13:45
BAndiT1983
nice!
13:47
BAndiT1983
se6ast1an: do you mean: "already a small amount of airflow"?
14:17
se6ast1an
yes
14:17
se6ast1an
thanks
14:21
BAndiT1983
ah, was just not sure at first
14:21
BAndiT1983
am off for a moment, will be back later
14:21
BAndiT1983
changed nick to: BAndiT1983|away
14:36
MichaelSchwarzma
left the channel
15:57
Bertl_zZ
changed nick to: Bertl
15:57
Bertl
mroning folks!
15:57
Bertl
*morning
15:58
se6ast1an
good morning
16:04
Bertl
se6ast1an: why is the power board temperature so 'blocky'?
16:05
se6ast1an
because "cat /sys/class/hwmon/hwmon0/temp1_input" only returns integer values
16:05
se6ast1an
is that not like its supposed to?
16:06
se6ast1an
divided by 1000 actually but still integer only, eg 34000, 35000...
16:06
se6ast1an
details see https://wiki.apertus.org/index.php/AXIOM_Beta/Temperatures
16:09
Bertl
well, integer values is fine, but they are in mili-degree celcsius
16:09
Bertl
for example on beta-b I see: 29500
16:10
Bertl
which means 29.5
16:13
Bertl
but your script simply throws away the fractional part
16:15
se6ast1an
ah
16:15
se6ast1an
then I need to improve it
16:15
se6ast1an
which line?
16:16
Bertl
line 36 has $(($PBTEMPRAW/1000))
16:16
Bertl
btw, it would be way better to log the raw values and do any post processing in 'post' :)
16:18
se6ast1an
ok
16:18
se6ast1an
thanks
16:20
illwieckz
left the channel
16:45
BAndiT1983|away
changed nick to: BAndiT1983
17:00
se6ast1an
MEETING TIME!
17:00
se6ast1an
good evening everyone, please pm me now to report in the usual manner
17:01
se6ast1an
metal_dent[m]: please go ahead
17:01
metal_dent[m]
hi everyone!!
17:02
metal_dent[m]
Last week, finally the communication problem solved and i was able to send and receive data between the remote and PC
17:02
metal_dent[m]
But after that solved i encountered another weird problem, i want to send a command string whose length was 18-20 characters
17:03
metal_dent[m]
but initially the script just hung then i found that if the length is <= 8 it was working perfectly. so i talked with BAndiT1983 and Bertl and we did some debugging and later confirmed that the python script which runs on the PC side has no problem
17:03
Dest123
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17:03
metal_dent[m]
the problem is somewhere in the USB code or the hardware.
17:03
illwieckz
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17:04
metal_dent[m]
so for the time being i'm splitting the string in 8 characters each (or less) and sending to the remote, so one problem down!!
17:04
metal_dent[m]
now i'm comparing the sequence number and checksum on remote and the ones coming from the PC then send "ACK" (or "NACK")
17:04
metal_dent[m]
getting some problem there also but just talked with Bertl and i think it'll solved now
17:05
metal_dent[m]
*it'll be
17:05
metal_dent[m]
that's it from my side! thank you :)
17:06
se6ast1an
many thanks!
17:06
se6ast1an
bluez_[m]: your turn
17:07
bluez_[m]
tx, hi everyone!
17:08
bluez_[m]
so this week bertl and I discussed with the openocd people regarding the best way to implement the debug interface that openocd supports
17:08
bluez_[m]
https://lore.kernel.org/patchwork/cover/1223367/
17:09
bluez_[m]
^^ they said this could be a possible implementation... currently not yet merged in linux kernel
17:09
bluez_[m]
but we can take inspiration from it and might implement something similar
17:09
bluez_[m]
but i couldn't look into this much this week
17:10
bluez_[m]
i mostly improved the driver code
17:10
bluez_[m]
https://github.com/Swaraj1998/axiom-beta-rfdev/commits/3e2910aee0796c4951cfc7160bdc1ec10f6994ae
17:10
bluez_[m]
look at the commits july 14th onwards
17:12
bluez_[m]
so majorly: i added a function to make sense of the status register bits... also added sysfs entry "statstr" to show the human readable interpretation of the status
17:13
bluez_[m]
i added code to register two fpgas... for two machxo2s...but currently both work for only one fpga which is selected by mux... so i was looking into how to handle muxes and everything
17:13
bluez_[m]
i struggled a bit to understand different muxes we have and how to use them in my driver...but i am much clear now
17:14
bluez_[m]
so this will be implemented this coming week
17:14
bluez_[m]
i also added a way to reset the fpga... currently done at driver exit
17:15
bluez_[m]
this week i will add a proper mechanism to switch between two mxo2s...and also start working on the debug interface as soon as possible
17:15
bluez_[m]
thats it from me!
17:16
se6ast1an
many thanks!
17:16
se6ast1an
preetimenghwani[: you are next, please go ahead
17:16
illwieckz
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17:17
preetimenghwani[
Thanks! Hello Everyone !
17:17
preetimenghwani[
So I spent most of the time gathering ideas on how throughput can be doubled and other features can be added and also discussed it with Bertl.
17:17
preetimenghwani[
It took quite some time as it required understanding of some part of the top module and a few other modules as well.
17:18
preetimenghwani[
I added a feature of Y subsampling and tested it on hardware too.
17:18
preetimenghwani[
Currently I am working on the task of doubling the throughput, also working on minimal framework which will be required for testing it.
17:18
preetimenghwani[
( I have added the project to wiki )
17:19
preetimenghwani[
Thanks a lot! Thats it from me :)
17:20
se6ast1an
many thanks!
17:20
se6ast1an
Great to see 3 projects have already been added to:
17:20
se6ast1an
https://wiki.apertus.org/index.php/GSoC_Projects
17:20
se6ast1an
megora and apoorva_arora whats your status?
17:22
se6ast1an
quick updates from me: I have been busy with temperature benchmarking in the AXIOM Beta CP enclosure with a 12V fan. There are more fans to test and of course its also interesting to see how each fan performs at different voltages and also how loud it is at such voltages. Documentation is work in progress here: https://wiki.apertus.org/index.php/AXIOM_Beta/Temperatures
17:22
apoorva_arora
ill update the wiki today
17:22
se6ast1an
great!
17:22
se6ast1an
any updates for us here as well?
17:23
apoorva_arora
Thanx, I spent most of the time in understanding how PS PL communuication over AXI works as I want to use the concept for testing. After spending lot of time and following a tutorial i incorporated my design a custome axi lite peripheral using vivado toolchain. I plan to use a baremetal code to test input output registers on ZYNQ.
17:23
apoorva_arora
meanwhile i started working on the third phase of the design
17:23
apoorva_arora
i.e scheduler
17:24
apoorva_arora
that schedules the incoming requests as per priority.
17:24
apoorva_arora
i implemeted the basic structure (https://github.com/Apoorva-ar/GSOC_2020/blob/master/Scheduler_master.vhd) and will be conducting testbench simulations today.
17:25
apoorva_arora
but ,main focus in the coming two weeks will be axi based hardware testing.
17:25
apoorva_arora
thats all from my side
17:25
se6ast1an
many thanks!
17:26
apoorva_arora
also can i use the axi perpheral from vivado toolchain?
17:26
Bertl
is it open source?
17:26
apoorva_arora
it is generated from tool itself and doesnt mention anything on the code
17:27
apoorva_arora
but i will have to see data sheet of the software to verify that
17:27
Bertl
needs to be at least a FOSS/OH compatible license
17:27
apoorva_arora
unlike lattice where they had specified on the code itself
17:28
apoorva_arora
okay i will look into that
17:28
Bertl
but there are several open source alternatives for an AXI lite peripherial
17:28
Bertl
(e.g. the one we use in the Beta gateware or the nMigen one)
17:29
apoorva_arora
okay
17:29
apoorva_arora
also
17:29
apoorva_arora
when we write data to an address via software
17:30
apoorva_arora
is the AXI master port on ZYNQ generating valid data signal
17:31
apoorva_arora
whenever software makes an update to the address
17:31
Bertl
not sure what you mean by that, but any write to one of the peripherial addresses will result in an AXI transaction between PS and PL
17:32
apoorva_arora
okay
17:32
se6ast1an
no updates from Bertl and BAndiT1983 today.
17:33
se6ast1an
We will host a hackathon with vup and anuejn in Vienna the first two weeks of August, some areas of work for the event: Micro V3 hardware, webui & nctrl <-> remote integration, Firmware 2.0 and maybe some nmigen gateware work.
17:33
se6ast1an
anyone else who wants to report?
17:34
se6ast1an
right then, quick meeting today :)
17:34
se6ast1an
many thanks to all participants!
17:35
se6ast1an
meeting concluded
17:35
Bertl
thanks!
17:35
preetimenghwani[
Thanks Everyone!
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20:29
Bertl
off for now ... bbl
20:29
Bertl
changed nick to: Bertl_oO
20:55
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21:08
mumptai
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22:34
BAndiT1983
changed nick to: BAndiT1983|away