#apertus IRC Channel Logs

panintended: any day is okay

I am waiting for an IKEA delivery between 9:00 - 13:00

off to bed now ... have a good one everyone!

BAndiT1983: panintended so in 25 minutes or in 1h25?

se6ast1an BAndiT1983 can we have it tomorrow or Wednesday 12:00 noontime UTC+2 time?

We can agree on another time as well. It's fine by me so long as I plan it. Another possibility would be today 17:00-18:00 UTC+2 for example.

What items will we discuss by the way?

am a bit out of the firmware topic, so would have also to check what's on the list, was looking more into BL-related stuff lately, but also occupied by other things a lot

main topic would be remote firmware and observer pattern remaining todos, next steps

panintended: please choose :)

won't work for me, as the appointment is at 16:00, don't know if i will back by then, but you both can discuss stuff and i can read and comment the logs later

every noon while from monday to friday is ok for me

?

Tomorrow 12:00 UTC+2

should be possible

also ok fr you panintended?

Yes, ok for me too

first cp enclosure fan test results are in: https://paste.pics/9LTS7

conclusion: just a small amount of airflow works to keep everything well within the healthy operation temperature range

se6ast1an: do you mean: "already a small amount of airflow"?

thanks

am off for a moment, will be back later

mroning folks!

good morning

because "cat /sys/class/hwmon/hwmon0/temp1_input" only returns integer values

divided by 1000 actually but still integer only, eg 34000, 35000...

well, integer values is fine, but they are in mili-degree celcsius

which means 29.5

ah

which line?

btw, it would be way better to log the raw values and do any post processing in 'post' :)

thanks

good evening everyone, please pm me now to report in the usual manner

hi everyone!!

But after that solved i encountered another weird problem, i want to send a command string whose length was 18-20 characters

now i'm comparing the sequence number and checksum on remote and the ones coming from the PC then send "ACK" (or "NACK")

*it'll be

many thanks!

tx, hi everyone!

https://lore.kernel.org/patchwork/cover/1223367/

but we can take inspiration from it and might implement something similar

i mostly improved the driver code

look at the commits july 14th onwards

i added code to register two fpgas... for two machxo2s...but currently both work for only one fpga which is selected by mux... so i was looking into how to handle muxes and everything

so this will be implemented this coming week

this week i will add a proper mechanism to switch between two mxo2s...and also start working on the debug interface as soon as possible

many thanks!

So I spent most of the time gathering ideas on how throughput can be doubled and other features can be added and also discussed it with Bertl.

I added a feature of Y subsampling and tested it on hardware too.

( I have added the project to wiki )

many thanks!

https://wiki.apertus.org/index.php/GSoC_Projects

quick updates from me: I have been busy with temperature benchmarking in the AXIOM Beta CP enclosure with a 12V fan. There are more fans to test and of course its also interesting to see how each fan performs at different voltages and also how loud it is at such voltages. Documentation is work in progress here: https://wiki.apertus.org/index.php/AXIOM_Beta/Temperatures

great!

Thanx, I spent most of the time in understanding how PS PL communuication over AXI works as I want to use the concept for testing. After spending lot of time and following a tutorial i incorporated my design a custome axi lite peripheral using vivado toolchain. I plan to use a baremetal code to test input output registers on ZYNQ.

i.e scheduler

i implemeted the basic structure (https://github.com/Apoorva-ar/GSOC_2020/blob/master/Scheduler_master.vhd) and will be conducting testbench simulations today.

thats all from my side

also can i use the axi perpheral from vivado toolchain?

it is generated from tool itself and doesnt mention anything on the code

needs to be at least a FOSS/OH compatible license

okay i will look into that

(e.g. the one we use in the Beta gateware or the nMigen one)

also

is the AXI master port on ZYNQ generating valid data signal

not sure what you mean by that, but any write to one of the peripherial addresses will result in an AXI transaction between PS and PL

no updates from Bertl and BAndiT1983 today.

anyone else who wants to report?

many thanks to all participants!

thanks!