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#apertus IRC Channel Logs

2014/05/20

Timezone: UTC


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Bertl
back now ...
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Bertl
off for a nap ... bbl
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Bertl
back now ...
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se6astian
good evening
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se6astian1
time for bed
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se6astian1
good night
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23:21
mookyj
Hi I gave the cmv12k-adapter-v1.1 a look over onthe schematic you might add a termination resistor to the lvds clk in to the sensor. as to the board it appears that it is a work in progress?
23:23
mookyj
are there any assembly views? it is not clear as to how you are getting heat away from the sensor. Forgive my ignorance as I get up to speed
23:24
Bertl
http://iloveubuntu.net/pictures_me/Aximom%20Alpha%20second%20prototype%20main.jpg
23:25
Bertl
without cooling, the sensor gets about 50-55°C, 45°C below the sensor
23:26
Bertl
with cooling (the big fan) it stays about 4-5°C above room temperature
23:32
mookyj
any metal contacting back of sensor?
23:32
Bertl
nope, nothing there in the alpha
23:32
Bertl
we plan to put a peltier at the back of the sensor in gamma
23:33
Bertl
btw, thanks for spotting the missing termination!
23:33
mookyj
dark current doubles roughly every 3-4°C
23:34
mookyj
its the stuff one worries about onthe siicon side, some library IP for io's have termination, some don't
23:34
mookyj
LVDS io's are a significant structure on the pad frame
23:35
intracube
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23:43
mookyj
that big connector in the center keeps you from heatsinking away from the sensor
23:43
Bertl
correct
23:44
mookyj
if you could dump into a xilinx on same board you could greatly reduce pin count assuming that you could do all your post processing at a single port 14-20 bits (depends on where you allocate the LUT)
23:45
Bertl
hmm?
23:46
mookyj
with John's (Andon) socket you might have room to machine a piece to pull heat out
23:47
mookyj
ah I went back and looked you don't use all the ports on the sensor
23:47
Bertl
currently not, this will change in the future (i.e. for gamma)
23:48
mookyj
there are so many tradeoffs for each solution, personally I have wanted to do a large format module head forever, and Panavision would never go for it
23:49
Bertl
but I'm not sure I can follow you with the 'dump into a xilinx'
23:49
mookyj
much easy to do that, and design the rest of the camera seperately, conquering the unique design issues
23:49
mookyj
my term for pulling all the data off the sensor
23:50
Bertl
well, that's what we do with 'the xilinx'
23:50
mookyj
get it off quickly then consolidate where you can to reduce complexity downstream
23:50
mookyj
could be any large fpga
23:50
Bertl
the sensor is directly connected to the zynq
23:51
Bertl
what would be the advantage to add another FPGA before that?
23:51
mookyj
if the fpga is right next to the sensor, you drive much shorter lines at 300-400mhz
23:51
mookyj
possibly
23:51
Bertl
okay, but I still have to get the data to the zynq then
23:53
mookyj
it is my thought that if the front end module grabbed the data, did the basic corrections unique to the sensor, then sent iot to the main board camera, you could design a camera that would adapt much easier to other sensor platforms
23:53
Bertl
but it would also consume twice the power, cost more money, produce more heat?
23:54
mookyj
yes your would, but you could in a way standardize the frame data, and use the Zynq to handle the camera functions, formatting, and outputs that are required
23:54
mookyj
probably not double. but likely more
23:55
Bertl
okay, but I don't see an advantage there ATM
23:55
mookyj
it would take some looking looking at the overall system to see what goes on be clock, per instruction to see if any savings owuld occur
23:57
mookyj
I am looking at it purely as getting data to something more universal, and reduce the signal loops at the sensor
23:57
mookyj
oops mis type; per clock
23:57
Bertl
we would have to process the same amount of data in any case
23:58
mookyj
anyway just a thought
23:58
Bertl
it just would get sent over LVDS twice
23:58
mookyj
well maybe, depends on where you combine the ports
23:58
Bertl
combine what ports?
23:59
mookyj
you have two 16bit ports from the sensor correct
23:59
Bertl
the sensor has 64 LVDS pairs in full conenction, we use 32 pairs in our setup
00:00
Bertl
16 top, 16 bottom
00:00
Bertl
each transfers up to 12 bit of a pixel from two rows
00:02
mookyj
this may make a better solution should you go 64, as you can combine reduce downstream pairs,m however i am not sure what limitations there may be on the processing side
00:02
mookyj
all good on paper :)
00:03
Bertl
well, it would require higher LVDS rates, so more power in the transfer, but less pins
00:03
mookyj
well I have to get home for dinner, thanks for the info, and helping me understand a bit more of the project
00:03
mookyj
agree on pwer
00:03
Bertl
no problem! thanks for looking into it
00:04
mookyj
Let me know when and where I can help!
00:04
Bertl
will do
00:05
mookyj
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00:21
Bertl
off to bed now ... have a good one everyone!