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| 00:33 | Bertl | off to bed now ... have a good one everyone!
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| 00:33 | Bertl | changed nick to: Bertl_zZ
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| 02:16 | mithro | Bertl_zZ / se6astian|away: Any idea why the PTN3363 seems to be so much cheaper than other equivalent parts?
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| 02:17 | mithro | Bertl_zZ / se6astian|away: Also, do you know of something like the PTN3363 that goes in the opposite direction?
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| 02:19 | mithro | Welp, you finally got me to install eagle too
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| 02:53 | sab_123 | hi
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| 03:02 | mithro | hi sab_123
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| 03:02 | sab_123 | hi
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| 03:02 | sab_123 | so you are in the apertus group now
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| 03:02 | sab_123 | :-)
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| 03:03 | sab_123 | I was just looking at what the apertus group was doing
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| 03:03 | sab_123 | and it seems a lot closer to the 360 project I wrote to you about
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| 03:04 | mithro | sab_123: no, we have "synergistic goals" so we try and work together
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| 03:04 | sab_123 | ah okay
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| 03:04 | sab_123 | anyway about the JPEG stuff
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| 03:04 | sab_123 | I have a repo setup
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| 03:04 | sab_123 | I put it in the timvideos group
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| 03:05 | mithro | ?
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| 03:05 | sab_123 | https://github.com/RacingTornado/JPEG_GSOC
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| 03:52 | mithro | Bertl_zZ: I think I misunderstood how VCCIO worked. It is supplied by the expansion board, to indicate voltage level to the FPGA - not the other way round?
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| 07:50 | John_K | mithro: correct. It is generated on the power board and supplied to microZed
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| 09:06 | Bertl | morning folks!
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| 09:07 | Bertl | mithro: it is the bank voltage of the FPGA
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| 09:07 | Bertl | i.e. it is supplied _to_ the plugin boards for level shifting purposes if required
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| 09:08 | Bertl | an FPGA on a plugin board could also use it for the I/O voltag when driving the LVDS pairs (as pairs or as single IOs)
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| 09:29 | mithro | Can I supply 3v3 to it then?
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| 09:29 | Bertl | if your I/O bank providing the LVDS pairs is 3V3, then you should do that
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| 09:30 | Bertl | although it will be unlikely that any beta will have 3V3 there, it will be 1V8 or 2V5
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| 09:32 | Bertl | but from the interface PoV it's okay to do that, as long as you are prepared to get 3V3 signals on the LVDS lanes when they are used as GPIOs
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| 09:33 | Bertl | the 8 GPIOs on each plugin module reference VCC, which will usually be 3V3
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| 09:35 | mithro | The 3v3 and 2v5 LVDS standards that Xilinx support are the same swing levels
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| 09:36 | Bertl | yep, the LVDS part is identical
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| 09:36 | Bertl | that is also true for Lattice and Altera btw
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| 09:37 | mithro | I'm assuming that 1V8 is probably different
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| 09:37 | Bertl | it is only relevant for LVCMOS 18/25/33
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| 09:38 | Bertl | LVDS has a swing of ~350mV around ~1.2V DC
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| 09:39 | mithro | Okay, I don't see vccio used in any of the schematics?
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| 09:39 | mithro | Isn't LVDS AC coupled?
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| 09:39 | Bertl | LVDS can be both
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| 09:40 | Bertl | if AC coupled, you need a reference bias
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| 09:40 | Bertl | we have a plugin module in the works which uses an FPGA. this one uses the VCCIO for supplying the bank
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| 09:41 | Bertl | but as I said, it is only really relevant if you use the LVDS pairs (or some of them) for LVCMOS
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| 09:44 | mithro | Okay
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| 09:44 | Bertl | so, if you have 1V8 handy, use that, if not, 3V3 should do as well
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| 09:45 | mithro | Our banks are running with a vccio of 3v3
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| 09:46 | Bertl | okay, then 3V3 is the correct voltage there
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| 09:46 | mithro | So I just need a 12v to 5v converter
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| 09:50 | mithro | Do you have trace width needed for impedance matching with ohspark?
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| 09:56 | Bertl | after long simulations (field solver) we went for an edge coupled micro strip with ground on the sides, where traces and spacing are 6mil
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| 09:57 | Bertl | note that this is only valid for the 4layer boards
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| 09:59 | Bertl | (where the prepreg is ~6.7mil)
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| 10:55 | mithro | Bertl: and for vias?
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| 13:06 | Bertl | mithro: for vias you need to be small (we use 8mil drill, 4mil annular) and you need two ground plane stitches nearby
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| 13:06 | Bertl | but whenever possible, avoid them
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| 13:07 | Bertl | also make sure that the ground flood on the signal plane has plenty of stitches to the ground below
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| 17:08 | se6astian | good evening
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| 17:11 | Bertl | evening se6astian!
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| 23:43 | Bertl | off to bed now ... have a good one everyone!
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| 23:43 | Bertl | changed nick to: Bertl_zZ
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| 23:45 | mithro | Bertl_zZ: The board doesn't have any via's on the high speed lines
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| 23:59 | mithro | Bertl_zZ: Looking at the HDMI design in Eagle, I confirmed the low speed traces are set to 8mil and the high speed to 6mil
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