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#apertus IRC Channel Logs

2020/11/19

Timezone: UTC


23:08
danieel
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danieel
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mumptai
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mumptai
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mumptai
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02:20
Bertl
off to bed now ... have a good one everyone!
02:21
Bertl
changed nick to: Bertl_zZ
06:10
BAndiT1983|away
changed nick to: BAndiT1983
07:28
se6ast1an
good day
07:28
se6ast1an
anuejn: hurray! thats great news!
07:31
comradekingu
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08:31
Bertl_zZ
changed nick to: Bertl
08:33
Bertl
morning folks!
08:55
anuejn
good morning
11:49
Bertl
off for now ... bbl
11:49
Bertl
changed nick to: Bertl_oO
12:51
RexOrCine
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14:29
se6ast1an
got a new TT15.5 draft from max, will review soon
16:00
anuejn
Bertl_oO: I have a problem with diamond:
16:01
anuejn
when I try to constrain an internal net with a clock constraint I get the error message "Source for clock clk not found in netlist."
16:02
anuejn
I guess the net is somehow optimized away during synth
16:03
anuejn
even when i attach keep=TRUE or syn_keep=1 as an attribute it doesnt work
16:03
anuejn
do you have any trick for that?
16:08
Bertl_oO
there are a number of attributes which might prevent that
16:08
Bertl_oO
(not sure for Lattice, never encountered the issue there)
16:09
Bertl_oO
for Vivado there is dont_touch and several keep variants
16:09
Bertl_oO
also it is important to have the attribute on the correct 'object'
16:09
Bertl_oO
i.e. a keep on a net doesn't do much, there you need a 'debug' attribute
16:39
anuejn
ah interesting, thanks
16:40
anuejn
in vivado keep on the wire does seem to help but in diamond sadly not
17:22
Bertl_oO
to complicate things, it also changes from tool version to version
17:27
anuejn
oh off
17:28
anuejn
luckily nmigen should handle that for me but sadly that is currently broken :(
17:28
anuejn
https://github.com/nmigen/nmigen/issues/546
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mumptai
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mumptai
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mumptai
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mumptai
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mumptai
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22:17
Bertl_oO
anuejn: so, all diamond problems solved for now?
22:17
anuejn
yup :)
22:17
anuejn
found a solution
22:18
anuejn
the default hierarchy seperator in sdl files is "." while EVERYWHERE ELSE it is "/"
22:18
anuejn
and "$" needs to be escaped even if you surround it by {}
22:18
anuejn
that tool...
22:21
Bertl_oO
it is always fun to demystify those tools ...
22:21
anuejn
s/sdl/sdc/
22:22
Bertl_oO
btw, did you read that article about decrypting Xilinx 7series bitstreams with the help of the FPGA?
22:25
anuejn
no?
22:25
BAndiT1983
changed nick to: BAndiT1983|away
22:25
Bertl_oO
https://www.usenix.org/system/files/sec20fall_ender_prepub.pdf
22:25
anuejn
sounds interesting
22:26
Bertl_oO
well, it boils down to letting the FPGA decrypt the bitstream word by word via the programming interface
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