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| 02:20 | Bertl | off to bed now ... have a good one everyone!
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| 02:21 | Bertl | changed nick to: Bertl_zZ
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| 06:10 | BAndiT1983|away | changed nick to: BAndiT1983
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| 07:28 | se6ast1an | good day
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| 07:28 | se6ast1an | anuejn: hurray! thats great news!
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| 08:33 | Bertl | morning folks!
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| 08:55 | anuejn | good morning
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| 11:49 | Bertl | off for now ... bbl
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| 14:29 | se6ast1an | got a new TT15.5 draft from max, will review soon
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| 16:00 | anuejn | Bertl_oO: I have a problem with diamond:
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| 16:01 | anuejn | when I try to constrain an internal net with a clock constraint I get the error message "Source for clock clk not found in netlist."
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| 16:02 | anuejn | I guess the net is somehow optimized away during synth
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| 16:03 | anuejn | even when i attach keep=TRUE or syn_keep=1 as an attribute it doesnt work
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| 16:03 | anuejn | do you have any trick for that?
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| 16:08 | Bertl_oO | there are a number of attributes which might prevent that
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| 16:08 | Bertl_oO | (not sure for Lattice, never encountered the issue there)
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| 16:09 | Bertl_oO | for Vivado there is dont_touch and several keep variants
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| 16:09 | Bertl_oO | also it is important to have the attribute on the correct 'object'
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| 16:09 | Bertl_oO | i.e. a keep on a net doesn't do much, there you need a 'debug' attribute
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| 16:39 | anuejn | ah interesting, thanks
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| 16:40 | anuejn | in vivado keep on the wire does seem to help but in diamond sadly not
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| 17:22 | Bertl_oO | to complicate things, it also changes from tool version to version
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| 17:27 | anuejn | oh off
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| 17:28 | anuejn | luckily nmigen should handle that for me but sadly that is currently broken :(
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| 17:28 | anuejn | https://github.com/nmigen/nmigen/issues/546
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| 22:17 | Bertl_oO | anuejn: so, all diamond problems solved for now?
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| 22:17 | anuejn | yup :)
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| 22:17 | anuejn | found a solution
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| 22:18 | anuejn | the default hierarchy seperator in sdl files is "." while EVERYWHERE ELSE it is "/"
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| 22:18 | anuejn | and "$" needs to be escaped even if you surround it by {}
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| 22:18 | anuejn | that tool...
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| 22:21 | Bertl_oO | it is always fun to demystify those tools ...
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| 22:21 | anuejn | s/sdl/sdc/
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| 22:22 | Bertl_oO | btw, did you read that article about decrypting Xilinx 7series bitstreams with the help of the FPGA?
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| 22:25 | anuejn | no?
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| 22:25 | BAndiT1983 | changed nick to: BAndiT1983|away
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| 22:25 | Bertl_oO | https://www.usenix.org/system/files/sec20fall_ender_prepub.pdf
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| 22:25 | anuejn | sounds interesting
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| 22:26 | Bertl_oO | well, it boils down to letting the FPGA decrypt the bitstream word by word via the programming interface
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