| 00:08 | danieel | left the channel |
| 00:34 | danieel | joined the channel |
| 00:34 | mumptai | left the channel |
| 00:48 | mumptai | joined the channel |
| 00:50 | mumptai | left the channel |
| 03:20 | Bertl | off to bed now ... have a good one everyone!
|
| 03:21 | Bertl | changed nick to: Bertl_zZ
|
| 07:10 | BAndiT1983|away | changed nick to: BAndiT1983
|
| 08:28 | se6ast1an | good day
|
| 08:28 | se6ast1an | anuejn: hurray! thats great news!
|
| 08:31 | comradekingu | joined the channel |
| 09:31 | Bertl_zZ | changed nick to: Bertl
|
| 09:33 | Bertl | morning folks!
|
| 09:55 | anuejn | good morning
|
| 12:49 | Bertl | off for now ... bbl
|
| 12:49 | Bertl | changed nick to: Bertl_oO
|
| 13:51 | RexOrCine | left the channel |
| 15:11 | RexOrCine | joined the channel |
| 15:29 | se6ast1an | got a new TT15.5 draft from max, will review soon
|
| 17:00 | anuejn | Bertl_oO: I have a problem with diamond:
|
| 17:01 | anuejn | when I try to constrain an internal net with a clock constraint I get the error message "Source for clock clk not found in netlist."
|
| 17:02 | anuejn | I guess the net is somehow optimized away during synth
|
| 17:03 | anuejn | even when i attach keep=TRUE or syn_keep=1 as an attribute it doesnt work
|
| 17:03 | anuejn | do you have any trick for that?
|
| 17:08 | Bertl_oO | there are a number of attributes which might prevent that
|
| 17:08 | Bertl_oO | (not sure for Lattice, never encountered the issue there)
|
| 17:09 | Bertl_oO | for Vivado there is dont_touch and several keep variants
|
| 17:09 | Bertl_oO | also it is important to have the attribute on the correct 'object'
|
| 17:09 | Bertl_oO | i.e. a keep on a net doesn't do much, there you need a 'debug' attribute
|
| 17:39 | anuejn | ah interesting, thanks
|
| 17:40 | anuejn | in vivado keep on the wire does seem to help but in diamond sadly not
|
| 18:22 | Bertl_oO | to complicate things, it also changes from tool version to version
|
| 18:27 | anuejn | oh off
|
| 18:28 | anuejn | luckily nmigen should handle that for me but sadly that is currently broken :(
|
| 18:28 | anuejn | https://github.com/nmigen/nmigen/issues/546
|
| 18:36 | mumptai | joined the channel |
| 19:10 | mumptai | left the channel |
| 19:25 | mumptai | joined the channel |
| 19:28 | mumptai | left the channel |
| 21:03 | mumptai | joined the channel |
| 23:17 | Bertl_oO | anuejn: so, all diamond problems solved for now?
|
| 23:17 | anuejn | yup :)
|
| 23:17 | anuejn | found a solution
|
| 23:18 | anuejn | the default hierarchy seperator in sdl files is "." while EVERYWHERE ELSE it is "/"
|
| 23:18 | anuejn | and "$" needs to be escaped even if you surround it by {}
|
| 23:18 | anuejn | that tool...
|
| 23:21 | Bertl_oO | it is always fun to demystify those tools ...
|
| 23:21 | anuejn | s/sdl/sdc/
|
| 23:22 | Bertl_oO | btw, did you read that article about decrypting Xilinx 7series bitstreams with the help of the FPGA?
|
| 23:25 | anuejn | no?
|
| 23:25 | BAndiT1983 | changed nick to: BAndiT1983|away
|
| 23:25 | Bertl_oO | https://www.usenix.org/system/files/sec20fall_ender_prepub.pdf
|
| 23:25 | anuejn | sounds interesting
|
| 23:26 | Bertl_oO | well, it boils down to letting the FPGA decrypt the bitstream word by word via the programming interface
|
| 23:56 | Spirit532 | left the channel |
| 23:57 | Spirit532 | joined the channel |